Other Parts Discussed in Thread: ADS1299
Hi E2E,
Good day.
Need your expertise with the ADS1298 cascaded configuration, here is the customer's query:
We have 16 ADS1299 ICs in our design and 5 ADS1298 ICs. The 16 1299s are divided into 8 blocks of 2 cascaded pairs all connected to a FPGA controller. The 5 1298s are divided into 1 independent IC (for a standard 10 lead ECG) and the remaining 4 into 2 blocks of 2 cascaded pairs. We originally had all the ICs operating on their internal clocks with one DRDY signal per pair. As we now understand, the difference in the internal clock causes incomplete conversions to be read when on the IC without the DRDY. So we connected the CLK lines together, set the IC with the DRDY signal with an internal clock and active clock output while the 2nd IC is set for an external clock. This worked great with the 1299s and all data can be read properly. We did the same change to the paired 1298s and are seeing bad conversion readings at consistent intervals (similar to the independent clocks but at larger intervals, around 1.5 Hz). Using a scope, we confirmed the clock output is present on the clock signal. We don’t know if there is something different between the 1299 and 1298 ICs regarding the cascade configurations to make this work. We think we have the correct HW connectivity now, but can you help us define the FW configuration and confirm the HW connectivity?
FYI – for the cascaded 1298s with independent clocks, we are able to read the analog input values in between the incomplete conversions “noises” data. But after changing to the Master/Slave clock config, we are not getting analog readings and are seeing the large false fluctuations at a repeatable rate.
Thank you for the assistance.
Regards,
Carlo
