DAC3482: Sample register cfg file

JH Shin

Guru 12645 points

Part Number: DAC3482

Hello,

My customer wants to use the DAC3482 with the conditions below.

- DACCLK = 491.52MSPS

- fDATA = 245.76MSPS, 16-bit word wide interface

- Input data = baseband data

- Interpolation = 2x

- fOUT = 122.88MHz

Could you please provide a sample register configuration file?

Thank you.

over 5 years ago

0 Kang Hsia over 5 years ago

TI__Guru* 82905 points

Hi JH,

Is the customer using the on-chip PLL mode, or using external clock at 491.52MSPS?

0 JH Shin over 5 years ago in reply to Kang Hsia

Guru 12645 points

Hi Hsia,

The customer is using the on-chip PLL mode.

Thank you.

0 Kang Hsia over 5 years ago in reply to JH Shin

TI__Guru* 82905 points

Hi JH,

The customer does not provide enough information for me to continue. If they are using on-chip PLL mode, then they will need to provide the reference clock information to the PLL.

They will also need to specify the sync mode for the DAC3482.

Please refer to section 7.5.2 of the datasheet for example routine. The customer may generate the configuration based on the configuration sequence below. They will need to modify the PLL reference clock and the P-scaler divider to fit the 491.52MSPS clock.

0 Kang Hsia over 5 years ago in reply to Kang Hsia

TI__Guru* 82905 points

Hi JH,

just checking if you have more information on customer's setup. Thanks.

0 JH Shin over 5 years ago in reply to Kang Hsia

Guru 12645 points

Hi Hsia,

Sorry for the confusion. The customer says they don't use the internal PLL.

DACCLK P/N input clock are 491.52MHz.

Please provide a sample register file for the reference.

Thank you.

0 Kang Hsia over 5 years ago in reply to JH Shin

TI__Guru* 82905 points

Hi JH,

no problem. What is the sync source needed? Dual or Single?

0 JH Shin over 5 years ago in reply to Kang Hsia

Guru 12645 points

Hi Hsia,

If not using the internal PLL, isn't it only possible in single sync source mode?

Regards,

0 Kang Hsia over 5 years ago in reply to JH Shin

TI__Guru* 82905 points

JH,

no, that's not a correct statement. You can have both options. Please ask the customer to read the datasheet and also below app note:

https://www.ti.com/lit/an/slaa584/slaa584.pdf?ts=1623377666071&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDAC3482%253FkeyMatch%253DDAC3482%2526tisearch%253Dsearch-everything

0 JH Shin over 5 years ago in reply to Kang Hsia

Guru 12645 points

Hi Hsia,

The customer will use single sync source mode.

Thanks.

0 Kang Hsia over 5 years ago in reply to JH Shin

TI__Guru* 82905 points

Hi JH,

Please refer the customer to below example file. As always, please ask the customer to refer to the datasheet to the DAC requirements, especially the initialization requirement for single sync source mode (i.e. non-repetitive frame signal).

Fullscreen DAC3482_FDAC_491p52MHz_2xint_NCO_122p88MHz_QMCon.txt Download

   x00	   xF18C
   x01	   x0000
   x02	   x8052
   x03	   xA001
   x04	   x4DF1
   x05	   x0000
   x06	   x3400
   x07	   xFFFF
   x08	   x0000
   x09	   x8000
   x0A	   x0000
   x0B	   x0000
   x0C	   x05A6
   x0D	   x05A6
   x0E	   x05A6
   x0F	   x05A6
   x10	   x3000
   x11	   x0000
   x12	   x0000
   x13	   x0000
   x14	   x0000
   x15	   x4000
   x16	   x0000
   x17	   x4000
   x18	   x205F
   x19	   x10F4
   x1A	   x4820
   x1B	   x0800
   x1C	   x0000
   x1D	   x0000
   x1E	   x1111
   x1F	   x8882
   x20	   x2201
   x22	   x1B1B
   x23	   x001F
   x24	   x1000
   x25	   x7A7A
   x26	   xB6B6
   x27	   xEAEA
   x28	   x4545
   x29	   x1A1A
   x2A	   x1616
   x2B	   xAAAA
   x2C	   xC6C6
   x2D	   x0004
   x2E	   x0000
   x2F	   x0000
   x30	   x61A8
   x7F	   x0001
CDCE62005 Registers
Freq:19.200000MHz
Address	Data
00		80400000
01		813C0001
02		81400002
03		C10C0003
04		00040004
05		29F01A55
06		44AF0006
07		165294A7
08		20001808

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DAC3482: Sample register cfg file