• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 946 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1258: Understanding DRDY

high speed guy
Expert 3505 points
Part Number: ADS1258

Hi,

I am working with an ADS1258 and had a question about the DRDY signal. I have four ADS1258 with the SPI interfaces all on the same bus, using the chip select to read each of them. I fan out the start signal to all four  ADCs and then read them when I receive the DRDY. My question is, will the DRDY clear (go back high) on the falling edge of SCLK if the ADC chip select is not low?  The reason I ask, is I need to know if I should wait for all the ADC DRDY signals before reading each of them.

 Thanks,

HSG 

  • +1
    TI__Guru 52496 points

    Hi High Speed Guy,

    Since all four ADCs are beginning conversions at the same time, the /DRDY signals should all go low around the same time (any differences would be due to mismatches between the clock sources). You could wait for all four /DRDY signals to go low before reading data or else monitor just one of the /DRDY signals and add a small delay to account for any differences in the clock frequencies.

    Additionally, one of my colleagues ran a test and found that /DRDY indeed is driven high after the first SCLK, even when /CS is held high.

    -Bryan