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ADS124S08: ADS12408 locking up.

GREG SHIPLEY
Intellectual 290 points

Part Number: ADS124S08

Using the ADS124S08.  I am able to write all registers and control the ADC via SPI.  I am currently connected to AIN0 for positive and AIN1 for negative of a differential signal.

I am set to use REF0 for my reference that is 5V (AVDD)

I am able to read a -0.038V signal with PGA of 1 accurately.  I am able to read the voltage with a PGA setting of 2 and it reports twice the ADC counts.  Higher PGA settings cause the ADC to lock up for lack of better description.  I can lower the voltage closer to zero and get it to work.  What am I missing on how the PGA works, I thought a setting of say 4 would simply take the ADC reading and return 4X the counts thus stating the voltage as 4X the input value and that would be -0.038V X 4 = -0.152V.  Perhaps I am missing how the PGA actually works or am I up against a voltage to reference limitation?

  • 0
    TI__Guru** 113765 points

    Hi Greg,

    Your basic understanding as to what to expect is correct.  However the voltage calculation should show the same result.  What changes is the full-scale range and the value of one code (LSB).  So using a gain of 2 results in twice as many codes but the calculated voltage is the same due to the fact that the full-scale range is 1/2.

    Usually when setting the reference to 5V the intention is to make a single-ended measurement.  Is that what you are trying to do?  If so, you must make sure that the input voltage is within the input range of the PGA.  For example, you cannot apply gain above 1 for a ground referenced input with the PGA enabled.  If you disable and bypass the PGA, the maximum gain that can be applied is a gain of 1.

    There are input voltage restrictions as given in the datasheet for input voltages with the PGA enabled.  What is the exact voltage referenced to AVSS for each input pin being used?  Is the input voltage within the proper range for the gains selected?

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Intellectual 290 points

    Thanks Bob, your explanation of the PGA makes sense.  As for what I am doing is reading a differential signal of a wheatstone bridge powered by 5V the same 5V that is AVDD.  This 5V goes to REF0+ and REF0- is AVSS which is what the 5V is referenced to so I think I am doing a true differential signal and not connecting AIN1 to AVSS rather connecting it to the one side of the bridge.  Each input pin should be a nominal 2.5V as with a standard wheatstone bridge configuration.  More tomorrow on this.  

  • 0 in reply to GREG SHIPLEY
    TI__Guru** 113765 points

    Hi Greg,

    I would verify that the bridge output is as you expect to make sure that there is not a miswiring issue.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Intellectual 290 points

    verified bridge output to be nominal 2.5V and it is differential (one side not tied to ground).  The 5V reference I have on REF0 is AVDD and referenced to AVSS.

    After hours and hours.  This is what I know.  a negative voltage on the CH1 differential input of more than -0.015V will lock the ADC up until it is removed or lowered in value closer to zero.  I cannot tell why or register status because the converter locks up.  No problem with positive voltages and the count converts to the voltage I see with a volt meter.  This is all with a PGA of 1.  Changing the PGA locks the converter up as well at lower voltages.  

    Allowing the channels to float (disconnected) locks the converter as well as does shorting the + and - of respective channels to each other.  I would expect that to read a near zero reading.  I am only using CH1, CH2 and CH3 in differential mode.

    I do not know why this is, I thought the hard part would be the SPI communication, it went smoothly.

  • 0 in reply to GREG SHIPLEY
    Intellectual 290 points

    Bob, a bit more information expanding on my last post.  If I set PGA = 2, I cannot put a positive voltage on CH1 set as differential of more than 0.030V.  doing so will make the data stream from the ADC go intermittent and eventually stop all together until the voltage is lowered,  I can put up to 0.127V on the channel if PGA = 1.  Again, negative voltages seem to lock it up as well.  My bridge is a standard setup with 350 ohm resistors and a 500 ohm pot to unbalance it and give me a differential signal.  

  • 0 in reply to GREG SHIPLEY
    Intellectual 290 points

    Aha!  To find the solution to a problem look within first.  Math error in my code with signed INT32 numbers.  that was the lock up. sure looked like the ADC but it was not.  One side note, I am running full duplex mode on three channels now with the ADC.  Thanks for the help.  anything else I will start a new thread.