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ADS1256: Input Buffer and PGA

Oliver Zander
Prodigy 50 points

Other Parts Discussed in Thread: ADS1256

Hi,

I have a question regarding the ADS1256 with enabled input buffer and PGA: when the buffer is enabled, the input voltage must remain below AVDD - 2.0V. Does that include the PGA? In other words: (Vin * PGA) <= (AVDD -2.0V)?

Figure 5 of the data sheet suggests that the PGA is after the input buffer. So I guess the answer is no. But I want to be 100% sure.

Thanks

Oliver

  • 0
    TI__Intellectual 1165 points

    Hi Oliver,

    Yes, with the buffer on, the input voltage must remain between the range of AGND to (AVDD - 2.0V), otherwise you will be outside of the absolute input voltage range of the device.  Exceeding the absolute input voltage range could cause damage to the device.

    Where the PGA comes into the equation is in the full scale input range calculation.  You will want to make sure that the input voltage (AINp-AINn) does not go beyond +/- 2*Vref/PGA.

    Please let me know if this helps and if you have any further questions.

    Best Regards,

    Marc

  • 0 in reply to Marc Royer
    TI__Mastermind 43915 points

    Hi Oliver,

    Just to add to what Marc Royer has stated - 

    - This is a common confusion we have had in the past with customers. When the buffer is enabled, the absolute input voltage range is AVDD - 2.0V. This spec relates each analog input channel to ground. For example, if you are using the ADS1256 with differential inputs, setting one input to 2.5V and the other at 3.5V (1V differential signal) is running the ADC out of spec. If you look at the block diagram on page 1 of the data sheet, you can see that the input drive buffer is prior to the PGA.

    - As Mark mentioned, the gain only comes into play when you are talking about the full scale input range.

    - So, to give you an example, if you have a 5V supply, the maximum input signal that can be applied to any of the analog input signals is 3V (5V - 2V = 3V) max. Therefore, if you use a 50mV input signal run in single ended mode in a gain of 64 (64 x 50mV = 3.2V), you would be fine as long as you have the proper reference voltage.

    Regards,

    Tony Calabria

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  • 0 in reply to Tony Calabria
    Prodigy 50 points

    Thanks for your quick repsonses!

    So my understanding is that the PGA setting has nothing to do with the input voltage range of the buffer, right?

    In my case: AVDD = 5.0V, Vref = 2.5V, differential mode, AINn = few mV, AINp can be up to 400mV, PGA is 8. Input voltages are < 3.0V, and 400mV * 8 = 3.2V (<2 Vref).

    Oliver

  • 0 in reply to Oliver Zander
    TI__Intellectual 1165 points

    Hi Oliver,

    Your understanding is correct.

    It looks to me like your case is OK.

    Please don't hesitate to contact us with any additional questions or if you need further help.

    Best Regards,

    Marc

  • 0 in reply to Marc Royer
    TI__Mastermind 44760 points

    Clarifying note for the strikethrough text in Marc's post above:

    Violating the “ABSOLUTE MAXIUM RATINGS” spec will cause damage. Violating the “Absolute input voltage” will cause erroneous conversion data because the buffer will saturate.

    It is not the voltage but the current that causes damage, as you can see from the “ABSOLUTE MAXIUM RATINGS” table. You can even exceed the “-0.3V to AVDD+0.3V” spec if you limit the current to 10mA.

    Regards,
    Chris