ADS8699: RVS pin level doesn't go high from low after /RST transition from L to H.

Hi Kazuya,

What's the output protocol selected by your customer when they did the experiments? Have the CONVST/CS and SCLK been kept high or low before sent the /RST low pulse to the ADC? or they went to high or low with ./RST pulse together? I believe it should be the 1st statement but want to confirm.

Best regards,

Dale

 Hi Dale,

 Thank you very much for your reply.

 They found the phenomenon just after  ADS8699 was powered up.

 They didn't write any data via SPI. So the device all internal registers are default value. 

>Have the CONVST/CS and SCLK been kept high or low before sent the /RST low pulse to the ADC?

-> Yes, both signal, CONVST/CS and SCLK have been kept low before sent the /RST low pulse to the ADC.

>or they went to high or low with ./RST pulse together?

-> No. CONVST/CS and SCLK have been kept low during /RST level transient.

 Could you please give me your reply?

 Thank you and best regards,

 Kazuya.

Hi Kazuya,

With CS held high, RVS reflects the status of the internal ADCST signal. In your customer's 2nd experiment, the ADC entered ACQ mode from RESET, so RVS went to high.

With CS low, the status of RVS depends on the output protocol selection.

Best regards,

Dale

 Hi Dale,

 Thank you very much for your kind supports.

 I think ADS8699 has 4 type of SPI protocol, SPI-00-s, SPI-01-s,SPI-10-s and SPI-11-s.

 Also SPI-00-s is selected just after the device powered up.

 Is the following sentence in the device datasheet,

"In order to exit any of the RESET states, the RST pin must be pulled high with CONVST/CS and SCLK held low.

After a delay of tD_RST_POR or tD_RST_APP, the device enters ACQ state and the RVS pin goes high."

not applied to the device when SPI-00-s is selected?

 Could you please give me your reply?

 Thank you again and best regards,

 Kazuya.

Hi Kazuya,

It should be applied to SPI-00 mode but the datasheet does not state clearly. Is the RVS correct with normal CONVST operation and without a RESET?

Best regards,

Dale

 Hi Dale,

 Thank you very much for your reply.

 Could I ask you the followings?

 If the answer to "Is the RVS correct with normal CONVST operation and without a RESET?" is yes, what is your answer?

 Can you say that the sentence "In order to exit any of the RESET states, the RST pin must be pulled high with CONVST/CS

and SCLK held low. After a delay of tD_RST_POR or tD_RST_APP, the device enters ACQ state and the RVS pin goes high." 

not applied to the device when SPI-00-s is selected? Or is this sentence incorrect? 

 Is there any other setting that causes the phenomenon the customer said?

 Thank you again and best regards,

 Kazuya.

Hi Kazuya,

The datasheet may have an incorrect description. The reason I asked you the question is to make sure if the the incorrect information is only related to the the RESET or the normal operation. I'm checking if it's possible to set up a bench to check. Is your answer "yes" to my question?

Best regards,

Dale

Hello Dale,

Thank you very much for your strong support

I asked the customer whether they have confirmed the RVS transient timing was correct with normal CONVST operation or not

when /RST low pulse is input or no input.

But they haven't checked it and they can't confirm it now due to some reason.

However they have confirmed that the first rising edge timing of RVS after powered up is 1.3ms after CONVST/CS first rising edge.

And the RVS timing is not changed regardless with /RST low pulse input or no input.

They want to see the actual waveform at the first RVS rising timing taken by TI.

Could you please send me correct waveform of the first RVS rising timing after /RST low pulse input?

Thank you again and best regards,

 Kazuya.       

Hi Kazuya,

I will set up a bench and do the measurement for your customer, it will take few days.

When you said " the RVS timing is not changed regardless with /RST low pulse input or no input", what's the status of CONVST/CS and SCLK?

Best regards,

Dale

Hi Dale

I will ask them it. Please give me a few days.

Thank you and best regards,

Kazuya. 

Hi Dale,

Thank you very much for your strong supports.

I confirmed them about the status of CONVST/CS and SCLK.

They input completely same waveform of CONVST/CS and SCLK for both case, /RST low pulse is input and not input.

Could you please let me know if you have anything should be confirmed them. 

I'm looking forward to receiving the result of your confirming ADS8699 RVS behavior using actual device.

Thank you again and best regards,

Kazuya. 

Hi Kazuya,

When you said "They input completely same ", were both CONVST/CS and SCLK signals kept in low or high status? thanks.

Best regards,

Dale

Hi Kazuya,

I did timing experiments on the ADS8681EVM with a controller card. ADS8699 is the 18-bit/100ksps version ADC in the ADS8681 family. Please see the details below:

Case1:  a low /RST pulse (200ns) was sent to ADS8699 when CONVST/CS was held high (SCLK either low or high).

              Result -  RVS output went to high after ~1.4ms delay. See the timings below, the 2nd screenshot is a zoomed-in timing of 1st screenshot.

Case2:  a low /RST pulse (200ns) was sent to ADS8699 when CONVST/CS was held low (SCLK either low or high).

              Result -   RVS output was always low.

Case3:  a low /RST pulse (200ns) was sent to ADS8699 while CONVST/CS was held low. Then, start normal conversions by sending CONVST/CS high pulses to the ADC.

   Result -  RVS output went to high after ~1.4ms delay after the 1st CONVST/CS high pulse (rising edge). Then RVS showed the behavior like the Figure 6-3 in the datasheet: the RVS went to high after ~0.64us delay while the CONVST/CS was activated from low to high, then the RVS went to low when the CONVST/CS was forced to low for retrieving the conversion data. See the timings below, the 2nd screenshot is a zoomed-in timing of 1st screenshot.

In a summary, what your customer observed for both case 1 and case 2 are correct. The datasheet does not describe clearly. I hope these help for you and the customer.

Best regards,

Dale

Hi Dale,

Thank you very much for your many strong supports.

The waveforms are very helpful for the customer and me.

Could I ask you an additional question?

When should CONVST/CS level be changed from L to H for the correct A/D conversion?

Is it after 1.4ms from /RST signal rising edge?

Thank you again and best regards,

Kazuya.

Hi Kazuya,

You can send CONVST/CS pulses to initiate conversions at any time after the ADC is reset. 

From the experiments, my suggestion is to start conversions by sending CONVST/CS pulses after reset, then start to monitor the RVS signal for each conversion after the 1.4ms delay(minimum). Please refer to my last two timing graphs.

Another option is retrieving the data after waiting for at least tCONV_max time after the CONVST/CS pulse (rising edge) is sent to the ADC. See Figure 6-3 in the datasheet.

Best regards,

Dale

Hi Dale,

Thank you very much for your strong supports.

I will tell the suggestions to the customer. It is very helpful for them and me.

Could I ask you a request?

Could you please consider modifying the current ADS8699 datasheet(SBAS777B) to clear RVS behavior description

after /RST goes high if the datasheet update timing coms?

Thank you again and best regards,

Kazuya.