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ADS131E08: ADS131E08 Register Read and Write Error

Jacob J
Prodigy 75 points
Part Number: ADS131E08

Hi,

I am using ADS131E08 and I am reading 8ch with default register settings. But I need change Config1 register. I am trying read and write something to config1 Regsiter but I get null in SDO pins. I add add my read code. Is there anyone who can help with the problem?

uint8_t readADS131E08_reg8bit(uint8_t regAdress, uint8_t numRead){ // numRead is number of register to read(byte)-1

//firts send sdatac

ads131_start_low();
ads131_csN_low();
sendSpiADS131(sdatac);
ads131_csN_high();
ads131_start_high();
delay_10us(1);

ads131_csN_low();
delay_10us(1);
sendSpiADS131(regAdress);
sendSpiADS131(numRead);
uint8_t readRegisiter = sendSpiADS131(0x00);
ads131_csN_high();

startContReadMode_ADS131E08();// default mode
return readRegisiter;


}

Thanks

  • 0
    TI__Guru 64186 points

    Hi Jacob,

    Thank you for your post.

    There are a couple things you can do to verify the device is functioning. First - can you check the /DRDY pin? Assuming you are providing the master clock (or using the internal clock) and START pin is high, the /DRDY pin should toggle at the default data rate. Next, can you read the default register settings before writing to the device? Is the ID register showing the correct value?

    Regards,

    Ryan

  • 0 in reply to Ryan Andrews
    Prodigy 75 points

    Hi Ryan,

    I look /DRDY pin and It looks normal date rate. When /DRDY is low, I begin read 8ch data. It is working. But I am not reading anything in config registers. I get only random values. I am trying to read with the above code. But it doesn't happen. So I dont read ID register.

  • 0 in reply to Jacob J
    TI__Guru 64186 points

    Hi Jacob,

    In that case, there could be a timing violation causing the RREG command to be ignored. Since this is a multi-byte command (opcode + n-1 registers), there is a minimum amount of time that sending each byte must take. This is called tSDECODE and is a minimum of 4*tCLK (see section 9.5.3.1).  Basically, if your SCLK frequency is greater than 2x the CLK frequency, you will need to add a short delay between byte transfers.

    Let me know what your SCLK and CLK frequencies are and we can confirm if this is the problem.

    Regards,

    Ryan