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ADC12QJ1600-Q1: CPLL jitter spec and its applicaiton & SYSREF windowing

Part Number: ADC12QJ1600-Q1

Hi, experts,

I'm assessing the ADC12xJ1600 for our LiDAR project, now I have 2 issues, could you please help me check in details? thanks a lot.

1. internal CPLL output jitter: from the d/s, the PLL additive jitter is >700ps. But for the 12bits ADC@1GSPS, my understanding is that the sample clock jitter should be <200fs to get the expected SNR performance. could you please help me confirm again if this internal CPLL can be used for this application? Also could you please help provide the detailed clock jitter or phase nosie requried for 12bits@1GSPS applicaiton case? it is appreciated if you can help provide the clock design solution here. thanks.

2. regarding the SYNREF, how to undestand the descriptions in d/s? could you please help give me one example to use SYSREF here? based on my understanding, the sync. clock from "SYSREF Windowing" block is relatched by the ADC core sampling clock, also since the  PLL refer clock phase is NOT aligned with the internal PLL output, so it sounds the SYSREF windowing block doesn't work if itnernal CPLL is enabled, correct? 

best regards,

Feng

  • Hi Feng,

    If you use the recommended the suppression for CPLL (9.5.7.7 CLK_CTRL2 Register) it will reduce the additive jitter by almost half. However for a time domain(LIDAR) application CPLL additive jitter is not a concern.

    Sysref windowing is used for deterministic latency. PLLREF_SE is set to zero by default which will pass the differential clock to the sysref windowing block. 

  • Hi Miguel, thanks for quick response.

    as the d/s claimed, the SNR spec. can be ~ 58dBc, may I know what the SNR is if we use internal CPLL clock genration?

    for the 2nd issue, my key concern is that since it is relatched with ADC sampling clock, the sysref windowing module is not useful here if the fine tuning for phase between PLL ref. clock and sysref is changed again by this re-latch. can you give one example for the complete operation of sysref windowing opeation and its impact on the JESD204? thanks.

    best regards,

    Feng 

  • Hi Miguel, could you please help us to evalute the clocking design requests of above two issuse in ADC12QJ1600 project? 

    1. if internal C-PLL is enabled, can you show the ADC SNR test spec. to us?

    2. if internal C-PLL is enabled, it means the SYSREF windowing doesn't detecting the setup/hold time spec. between SYSREF+/- and ADC smapling clock since the ADC sampling clock is sourced from C-PLL and its phase could not be aligned with the PLLREF clock. also the follow part has one re-latch circuit, so the question is that if this SYSREF windowing can work well if C-PLL is enabled? could you please help share the test report under this condition? we need this feature for clocking solution evalution urgently. please help extend your support, thanks.

    Best regards,

    Feng

  • Hi Feng,

    there are datasheet (Figure8-38.....)plots in the datasheet that show CPLL performance.

    Using sysref windowing will give you a deterministic/constant latency from the ADC to the FPGA across temperature/voltage. If you don't use sysref window then your latency can change since it's not constant, for example if you power up/down the device, latency can change as it's not deterministic.

  • thank Miguel.

    in the d/s, the SNR spec. is measured with disabling internal CPLL. could you please help run it in TI EVM with internal CPLL and share the SNR performance? thank a lot.

    btw, for JESD204 standard, the setup/hold timing between SYSREF+/- and ADC sampling clock is critical to secure the deterninistic latency. but in the function block for ADC12QJ1600, why tthe "SYSREF windowing" block fine tunes the phase between SYNREF+/- and PLLREF NOT between SYSREF+/- and ADC sampling clock? could you please help elaborate it? thank a lot.

    best regards,

    Feng

  •  SNR is measured when CPLL disabled. can you plesae help share the SNR/SINAD test data when CPLL is enabled in ADC12QJ1600 EVM board? thank a lot.

  • Hi Feng,

    these are just a few CPLL AC plots but more are in the datasheet. Please keep scrolling on plot list.

    Yes, sysref and ADC clock are critical for deterministic latency. CPLL generates the Fs clock which was derived using the refclk. Since the refclk is at much lower frequency setup and hold time is much more forgiving. you only need to align the refclk with sysref when using the CPLL.

  • Thanks.

    So the CPLL has fixed phase error beteen the reference clock and CPLL output fs? since the JESD204 requried the setup and hold spec. between SYSREF and ADC sample clock. So i think the CPLL should be one zero delay PLL which has phase alignment between REFCLK and CPLL output clock, is it correct? 

    btw, why in the diagram block, the ADC sample clock is re-latched? thanks.

    Best regards,

    Feng 

  • Hi Feng,

    phase error between ref clock and out sampling clock will be the same. ADC clock is not re-latched its the sysref frequency.   

  • Hi Miguel,

    So I can understand the CPLL is one zero delay output with the same phase edge, is it right?

    For the relatched, please check the clock subsystem in the d/s, the SYSREF signal after "SYSREF windowing" block is relatched by the ADC sampling clock shown in below figure, can you please help check why this relatch is used? it sounds this relatch would impact the setup/hold timing between ADC sampling clock and SYSREF signal. thanks.

    best regards,

    Feng

  • Hi Miguel, any update for this "RELATCH SYSREF" function? 

    Thanks.

    Feng

  • Re-lataching Sysref is to align sysref to Fsclock. Relatching will not affect your setup and hold times.

  • One question: if the relatching change the setup/hold timings between sysref and fsclock? the sysref windowing module is fine turing the setup/hold timings between sysref and fsclock/PLL_REF, but the relatch would change the timing between sysref and fsclock.

    best regards,

    Feng

  • relatching does not change the timing.