• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 490 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC12DJ3200: NCO synchronization problem with multiple ADCs

Amy Luo
Expert 6895 points
Part Number: ADC12DJ3200


Hi team,

One of our customers uses 2 pieces of ADC12DJ3200 and uses the mixer inside to complete the DDC operation. When trying to synchronize the NCO of two ADCs, it cannot be completed.

The customer tried to synchronize using SYCN signal and using SYSREF (AC-coupled), respectively, as described in the datasheet, but neither method did the synchronization between the two ADCs.

The NCO for 2 channels on the same ADC is synchronized.

The customer after performed logical "AND" operations on sync signal through the FPGA and then sends it to two ADCs separately. 

When the frequency of the NCO is set to 0, the consistency of the two ADCs is good.

What special attention needs to be paid to synchronizing multiple ADCs?

PS: ADC sample rate is 2.4 GHz, sydref frequency is 4.6875MHz, and NCO frequency is 1.8 GHz

Best Regards,

Amy Luo

  • 0
    TI__Mastermind 20541 points

    Hi Amy,

    Can you please let us know the JMODE the customer is using and also the K value being used. ?  In the steps below is the customer setting the NCO_SYNC_ILA to 1 after device has been programmed for normal mode? and SYNC signal has the to meet the setup and hold time.

    NCO synchronization using JESD204B SYNC signal (SYNCSE or TMSTP+/–):

    1. Device must be programmed for normal operation

    2. Set NCO_SYNC_ILA to 1

    3. Set JESD_EN to 0

    4. Program FREQAx, FREQBx, PHASEAx and PHASEBx to the desired settings

    5. In JESD204B receiver (logic device) deassert SYNC signal by setting it high

    6. Set JESD_EN to 1

    7. Assert SYNC signal by setting it low in JESD204B receiver to start CGS process

    8. After achieving CGS, deassert SYNC signal by setting it high at the same time for all ADCs that are to be

    synchronized and verify that SYNC setup and hold times are met (specified in Timing Requirements)

    Regards,

    Neeraj