ADS1259: Timing to Exit Power Down ( tRHSC )

Hi Albert,

Welcome to the E2E forum! I would first recommend that the RESET/PDWN pin have a pullup connected so that it doesn't float on initial power up.  I'm not totally clear on what you are doing.  The normal operating state of the ADS1259 would be to set the RESET/PDWN pin high.  If you pulse the RESET/PDWN from high-low-high the device will reset.  If you hold the pin low, the ADS1259 will go into power down mode.  Just so that I'm clear, is the RESET/PDWN pin high, then are you setting it low for 2^16 clocks cycles?

After the 2^16 clock cycles low for the RESET/PDWN and you bring the RESET/PDWN pin back high, you need to wait another 2^16 clock cycles before attempting to communicate to the ADS1259 using SPI.  Have you verified all your timing with an oscilloscope or logic analyzer?  And do you have any shots that you can provide?

Best regards,

Bob B

Hi Bob,

Thank you for replying back.

- We don't have a pull up on the RESET/PDWN pin.

- Yes, I understand that if you pulse this pin from high to low to high, the ADC chip will reset, and if you hold it low longer than 2^16 cycles the ADC chip will enter power down mode.  And if it does enter power down mode, you will need another 2^16 cycles of RESET/PDWN pin held high in order to exit power down mode.

- Yes, I have checked all timing with a logic analyzer and they all meet the spec.

- Below is an image of the events of initialization after power up.

   a. Power is applied, and all power are good.

   b. FPGA is done programming, and can control Outputs.

   c. FPGA holds RESET/PWDN signal high for 9.18 msec (longer than required 8.88 msec) to allow the ADC chip come out of power down mode.

   d. FPGA holds RESET/PWDN signal low for 0.752 usec (longer than required 0.543 usec) to allow the ADC chip to reset.

   e. FPGA starts initializing the Programmable Gain Amplifier (PGA) chip through the common SPI bus.

   f. FPGA starts initializing the ADC chip through the common SPI bus. (longer than required timing).

Hi Albert,

I think I understand now what you are doing procedurally.  Are you using the PGA280?  Can you send me the Saleae data files for me to review the timing?  I want to verify the CS timing with the SCLK to the ADS1259.

Best regards,

Bob B

Hi Albert,

I reviewed the data and I agree that it doesn't quite add up.  According to the configuration you are using an external clock source.  Have you verified the frequency?  Also I see some added startup delay.  I would suggest reviewing the section CONVERSION SETTILING TIME on page 24 of the ADS1259 datasheet.  Note that the conversion time is the combination of the data in tables 8 and 9.

I would suggest that you try running the device without the actual configuration changes to verify the device timing in default setup mode.  In other words, just reset the device and then set the START pin high to determine the actual conversion time with default settings.  This would give us some comparison data to look at.

In the mode you are configuring I would expect approximately 540us (sinc2 filter and startup delay) conversion time, but this will extend if the external clock frequency is slower than the 7.3728MHz nominal rate.

Best regards,

Bob B 

Hi Bob,

No, per configuration, we are using the internal clock (7.3728 MHz) as reference.  I am writing 0x56 to register address 0x1.

Yes, I understand the total conversion time (from START to DRDY) is the START Delay plus Settling Time which we have configured and calculated to be around 0.8 msec.  ( The default is a total of around 100 msec. )

Yes, I have previously ran some tests just toggling the reset signal and without the ADC being configured, and the ADC does use its default values. ( checked by verifying the total conversion time being around 100 msec. )

No, the mode we are trying to configure is:

   Initial START Delay: 2048 => 278 usec

   Settling Time: Sinc 2 Filter & 14,400 SPS => 563 usec

Thus, the total conversion time from START to DRDY should be around 841 usec.

I have extended the Exit Power Down Mode time (tRHSC) from the original 9 msec to 20 msec, and all ADC chips can now reliably get initialized.

When configured between 9, 10, 11, 12, and even 15msec, I still have some times where the ADC chips cannot be properly initialized.  The longer the time was extended, the more often the ADC chips can be properly initialized.

Per the datasheet, the minimum required time is around 8.88 msec (2^16 * 1/7.3728), but 9 msec should already meet this requirement.

Please advise on what are your thoughts or any suggestions.

Thanks,
Albert

Hi Albert,

I did misread the register 1 setting which would set the delay to 2048 tclk.  However, register 2 is being set to 0x57.  The bits 7 and 6 are read only, but I assumed that based on that information you are using an external clock.  Apparently this was a bad assumption.  If you do connect an external clock the ADS1259 will switch to the external clock source automatically.

So, I guess we can agree that the timing is correct for the given configuration and the plots sent, but the question still remains regarding the timing of the dual function RESET/PWDN pin.  

I think what is happening, although I currently do not have a way to verify, is that the initial power up POR never completes as the device is held in a power down state.  The initial POR also takes 2^16 clock cycles to complete after the power supplies have reached nominal operating voltage.  This internal timer allows time for the ADS1259 to have settled supplies and to startup the internal oscillator and read configuration information for the device.  This action does not fully complete as the device is being held in a powered down state.  There are a number of internal reset signals for the device and from the device design document it is not clear as to whether or not the initial power up reset needs to complete before the next sequence is allowed to start.  So it is quite possible that from the time RESET/PDWN goes high it could take 18ms before communication is reliable.

Normally what would be done is a weak pullup be placed on the RESET/PDWN pin so that the startup follows the supply.  After both the AVDD and DVDD have reached the voltage levels shown in figure 49,  2^16 tclk periods later the POR would release.  At this point you should be able to communicate to the ADS1259.  There is really no need to hold the device in a powered down state at that point of startup because to enter PDWN the device needs to be released from POR and operating so as to be able to internally count 2^16 clock cycles to recognize the power down condition.

So it is not entirely clear as to the actual operating state due to the initial POR and state of the RESET/PDWN pin so it is difficult to fully predict the timing action.  If the RESET/PDWN pin tracks with the DVDD (and AVDD is also present) then the device should be able to communicate 2^16 clock periods from that point.  I would not add any additional reset as that would be redundant following the initial POR and will only add to the internal reset uncertainty.

Best regards,

Bob B

Hi Bob,

Correct, the plot I sent you does properly initialize the ADC, and has a total conversion time of 0.8 msec.

But with the same sequence and board and setup, sometimes the ADC doesn't get initialized at start up.

( When I get a chance, I can send you some further data. )

Ok, I think I understand what you are saying.

The ADC chip has an "internal reset" per the Power-On Sequence that needs 2^16 cycles which is around 8.88 msec.  And this "internal reset" logic cannot start if the ADC chip is held under power-down mode (RESET/PWDN pin held low longer than 2^16 cycles, around 8.88 msec).  I could not find any statement that supports this in the datasheet, please advise.

Thus, if this happens (if the ADC chip is held under power-down mode at start up), I would need to set the RESET/PWDN signal high for 8.88 msec to wait for the ADC to exit "internal reset" mode and wait another 8.88 msec to allow the ADC exit "power down" mode. Is this right?

Yes, I don't have a pull up resistor on the RESET/PWDN pin, it is floating when the FPGA is being reprogrammed after board power is applied.  Which potentially can cause the ADC to enter "power down" mode.

Is there any way TI can confirm that this is the case? Are there experiments being done? If it is true, I believe the datasheet needs to be updated to clarify this.  Please kindly advise.

Thanks,
ALbert

Hi Albert,

I will need to get ahold of the digital designer to see if he can shed any more light on what may happen with the sequence you are using.  Consider that the original design of the device is based on certain assumptions on our part.  One of the assumptions is that when powering on the ADS1259 it is intended to be placed in an operating condition as opposed to a power down condition otherwise why power it up in the first place.  That said, I agree that the datasheet is not clear.  What it does state is that 2^16 clock cycles after the RESET/PDWN is held low, the device powers down.  This means that the internal devices also power down including the internal oscillator preventing the internals from being able to count cycles before releasing from the POR state.

One further bit of information I will need to tell the designer is how you are determining this timing with respect to operation.  Are you powering up the system from a cold start state (power has been off for a while and any available charge has drained from caps) or are you doing power on-off-on type cycle tests?  If it is the latter, what is the off time?

Best regards,

Bob B

Hi Bob,

Thank you for digging in to this for me, really appreciate it.

I am doing power cycles with around 1 sec duration in between off and on.

Yes, please help ask the designer if this is what really happens when the RESET/PWDN signal is being asserted low during power up.

And that the ADC chip will 1st come out of "internal reset" for around 9msec, and then another 9msec to exit power down mode, in order to start communicating to the ADC chip through SPI bus.

Thanks,

Albert

Hi Albert,

I requested further information from the designer and will update as soon as I can get a response back.

Best regards,

Bob B

Thank you Bob!!

Can you ask the designer if below sequence is enough to have the ADC reliably power up for our situation.

I have tested it with below sequences, and have not yet seen any issues.

1. ADC power is all up and RESET/PWDN pin is floating (most likely being detecting low).

2. Wait for 400 msec until FPGA is done programming.

3. FPGA starts to control RESET/PWDN signal and asserts high for 20 msec.

    (please note, before when we saw that the ADC issue where it was not accepting configuration properly is when this time was held only for 9 msec, instead of this new 20 msec.)

4. FPGA then holds RESET/PWDN low for 750 nsec, and then sets it back high.

5. FPGA then waits 63 usec until it starts initializing the ADC through SPI bus.

Thanks,
Albert