vhdl source code and .ucf file for vertex 4

payal singhai

Other Parts Discussed in Thread: ADS4149, ADS6445, ADS6149

i am using tsw1200evm with ads6425evm.i followed the link http://www.xilinx.com/support/documentation/application_notes.htm for vhdl source code as suggested by email technical support of ti.but .ucf file given in link is for vertex5.kindly send me .ucf file and vhdl source code for given boards.an immidiate action is required because i can't proceed further with my project without these documentation.

thanks

over 15 years ago

0 Richard Prentice over 15 years ago

TI__Mastermind 29220 points

Hi,

i cannot provide support for a Xilinx application note, especially when our TSW1200 does not implement the deserialization the way the Xilinx document recommends.

We do provide the Verilog source code for the TSW1200 FPGA upon request, to a separate email address if provided, but with the understanding that the FPGA firmware was not developed for public support and is to be accepted 'as-is' for people who wish to consult it for a leg up with their own design. The Verilog was not documented or commented for public use, and the definition of the register space controlling the firmware is very tightly tied in with how the Xilinx cells operate. Also, the code is much more complex than would otherwise be needed for a single ADC interface because the TSW1200 has to support so many different data formats.

The TSW1200 Capture Card hardware and User Interface are made available to support evaluation of our many ADC EVMs, and it does that. If you are doing something that requires redesigning or modifying the code, that is outside the normal scope of the EVMs.

Regards,

Richard P.

0 Victor Levandovsky over 14 years ago in reply to Richard Prentice

Intellectual 575 points

Hello, Richard

Now we develop some project with TI ADC/DAC and Xilinx.

How to get Verilog/VHDL code for TSW1200?

-- Best Regards,

Victor

0 Richard Prentice over 14 years ago in reply to Victor Levandovsky

TI__Mastermind 29220 points

Hi,

There are *two* separate source code folders for the TSW1200, depending on whether the TSW1200 is to be used with a serialized format such as from the ADS6445 or whether the TSW1200 is to be used with a parallel LVDS format such as ADS4149. Both bit files are stored in the eeprom on the TSW1200 and jumper J11 on the TSW1200 selects which bit file is used and thus which data format the FPGA will be expecting.

Which ADC EVM would you considering, so that I may know which source code folder you need? And please provide an email address that I can send it to.

Regards,

Richard P.

0 Victor Levandovsky over 14 years ago in reply to Richard Prentice

Intellectual 575 points

Hello, Richard...

Thank you very much for your reply.

We are planning to use parallel LVDS ADC.

We would like to receive a examples/source codes for parallel LVDS.

My e-mail is victor{at}pcisystems(dot)com

Kind Regards,

Victor Levandovsky

0 Richard Prentice over 14 years ago in reply to Victor Levandovsky

TI__Mastermind 29220 points

Sent to the address provided.

Regards,

Richard P

0 Payam Aminian over 14 years ago in reply to Richard Prentice

Prodigy 30 points

Hello, Richard

Now we develop some project with TI ADC/DAC and Altera.

I use ADS6149 and How to get Verilog/VHDL code for TSW1200 to interface with this ADC?

-- Best Regards,

payam

0 Payam Aminian over 14 years ago in reply to Payam Aminian

Prodigy 30 points

Dear Richard

my email is : payam.aminian@gmail.com

0 Fred L Skalka over 13 years ago

Intellectual 260 points

I am planning on using the ADS4149 with a xilinx Kintex-7. The board is almost done. Can you please send me the source code spoken of in this discussion to fred.skalka@mistrasgroup.com

thanks.

0 Richard Prentice over 13 years ago in reply to Fred L Skalka

TI__Mastermind 29220 points

Sent to the address provided.

Regards,

Richard P.

0 Fred L Skalka over 13 years ago in reply to Richard Prentice

Intellectual 260 points

Hi Richard:

I did not get the code yet: Please try again to

fred.skalka@mistrasgroup.com

Also, just to be sure I get it, please send to

fskalka50@yahoo.com

I figure one of them should get through.

thanks

Fred

0 Richard Prentice over 13 years ago in reply to Fred L Skalka

TI__Mastermind 29220 points

Sent to these two addresses. Did you check the junk folder to see if the last one got put there? I checked my sent folder, and I also didn't see a bounce-back.

Regards,

Richard P.

0 Fred L Skalka over 13 years ago in reply to Richard Prentice

Intellectual 260 points

Nothing in my junk e-mail box. I tried forwarding it from home email and it did not go through either. i will have to talk with our IT folks.

thanks.

0 Richard Prentice over 13 years ago in reply to Fred L Skalka

TI__Mastermind 29220 points

Hi,

Take a look at the file extensions in the zip file that got through to the second address and ask your IT if any of them are flagged as potentially malicious. Besides the .v and the .ucf there are a few other file extensions in the zip file that Xilinx uses. Usually I see no trouble with them. If I try to send zip files with .exe or .dll then I often have to change the extension to something like .eexxee to artifically get it past screening for potentially malicious code. But I haven't seen any issues with the file extensions in this zip file before. But some places may also have concerns about zip files in general. Glad you got it finally.

Regards,

Richard P.

0 alex chu90 over 11 years ago in reply to Richard Prentice

Prodigy 10 points

I have got a TSW1200 evm board with several high speed ADC evm boards of ADS55xx and ADS6xxxx. could you please send me the fpga source code (and also .ucf file) to : mimitech AT gmail . com

I need the both DDR and LVDS mode source code. thanks very much!

0 Richard Prentice over 11 years ago in reply to alex chu90

TI__Mastermind 29220 points

Hi,

Sent to the address provided.

Regards,

Richard P.

0 Gilberto Casillas over 10 years ago in reply to Richard Prentice

Prodigy 40 points

Hello,

Is it possible that I receive a example code? I am going to use an ADS6445 card and a Spartan 6 Xilinx FPGA. My e-mail address is gacp@geofisica.unam.mx. Thank you very much in advance

0 Gilberto Casillas over 10 years ago in reply to Richard Prentice

Prodigy 40 points

Hello Richard

I am planning on using the ADS6445 with a xilinx Spartan 6. Can you please send me the source code spoken of in this discussion to gacp@geofisica.unam.mx or/and to gilcasillas@gmail.com ?

thank you very much

Gilberto