ADC12DJ3200: ADC sync pin toggles after sometime, i.e JESD link goes down.

Hi Naveen,

Section "8.3 Initialization Set Up" of datasheet shows how to configure the ADC.

What is your FPGA clock frequency(Fs*2.5/40)?

When is loses lock can you read reg 0x208 and see what bit 2 is set too?

Do you recalibrate the ADC?

For sysref calibration can you select sysref_zoom=1 instead on "0". At higher frequencies it recommended to set it to 1.

Hi Miguel,

What is your FPGA clock frequency(Fs*2.5/40)?

Ans: 156.25 MHz

When is loses lock can you read reg 0x208 and see what bit 2 is set too?

Ans: It is reading as 0x6C

Do you recalibrate the ADC?

Ans: No, what are the steps needed for recalibration?

For sysref calibration can you select sysref_zoom=1 instead on "0". At higher frequencies it recommended to set it to 1.

Ans: I am writing 0x68 in 0x0029

Since the ADC is reading 1 for bit 2 that means that the serdes PLL is still locked therefore you are not losing your clock to the ADC.  

Since your not recalibrating then it's not a problem. 

Is the LMK providing your sysref and/or FPGA clock? Can you probe at the output pins to see if you are getting a signal out? If FPGA clock is not getting to FPGA then you can lose lock.

Can you give me a block diagram(ADC,LMK,LMX,FPGA) of how your setup looks like?

Is the LMK providing your sysref and/or FPGA clock?

Ans: Yes

Can you probe at the output pins to see if you are getting a signal out? If FPGA clock is not getting to FPGA then you can lose lock.

Ans: I am getting signal which is going to FPGA

Below is how setup looks like.

Below are the steps for initialization of ADC

0x0000, 0x30
0x0002, 0x00
0x0003, 0x03
0x0004, 0x20
0x0005, 0x00
0x0006, 0x05
0x000C, 0x51
0x000D, 0x04
0x0010, 0x00
0x002A, 0x00
0x002C, 0x00
0x002D, 0x00
0x002E, 0x00
0x0030, 0xC4
0x0031, 0xA4
0x0032, 0xC4
0x0033, 0xA4
0x0038, 0x00
0x003B, 0x00
0x0060, 0x01
0x0200, 0x00
0x0061, 0x00
0x0201, 0x05
0x0202, 0x1F
0x0203, 0x01
0x0204, 0x02
0x0205, 0x00
0x0062, 0x01
0x0061, 0x01
0x0213, 0x07
0x0029, 0x20
0x0029, 0x68
0x0048, 0x0F
0x0206, 0x00
0x0207, 0x00
0x0208, 0x00
0x0209, 0x00
0x0200, 0x01
0x006C, 0x00
0x02B1, 0x05
0x02B0, 0x01
0x006C, 0x01
0x02C0, 0x00
0x02C1, 0x1F
0x02C2, 0x00

And my SYSREF is continuous

For the Alarm bit register(0x2c2) does CLK_ALM(bit 0) alarm turn on as well? if clock is lost for an instant this can cause sync loss. 

Can you also try running without sysref calibration and see if you still lose lock.

For the Alarm bit register(0x2c2) does CLK_ALM(bit 0) alarm turn on as well?

Ans: Yes, I was getting 0xD in 0x2C2.

Can you also try running without sysref calibration and see if you still lose lock.

If I don't do sysref calibration link fails on power on sometimes.

What should be values in sysref capture position register?

I am getting 0x8D in 0x02C, 0x61 in 0x02D, 0x8C in 0x02E.