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jesd link parameter change and reflection in gtx transceiver

mohammad yasin chintapalli
Prodigy 20 points
Part Number: TI-JESD204-IP
Other Parts Discussed in Thread: AFE7950

Hi,

I am working on the TI JESD IP core.

i successfully created a reference design for ZC706 and TIJESD ip core.

The default jesd link parameters are 88210 for both tx/rx.

my requirement is tx-44210, rx-22210.

I changed according in "jesd_link_parameters.h" . but gtx transceiver is at its default settings and errors generated in refdesign_rx.sv.

Please help me the procedure to  change parameters dynamically and generate the bit file successfully.

yasin.

  • 0
    TI__Mastermind 38890 points

    Hi Yasin,

    Can you please let us know what TI ADC device you are using to implement the IP?

    Thx,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 20 points

    hi,

    i am using AFE7950 EVM .

  • 0 in reply to mohammad yasin chintapalli
    TI__Mastermind 38890 points

    Thank you Yasin! I will get this assigned appropriately for a response.

  • 0
    TI__Genius 10865 points

    Hi Yasin,

    Apart from changing "jesd_link_parameters.h", you have to change the transceiver settings as well. Open the transceiver wizard in Vivado and change it to 4 lanes for Tx and 2 lanes for Rx. The TI IP will work with correctly configured transceiver.

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    Prodigy 20 points

    hi vijay,

    I am using vivado 19.1 and when i open gtx wizard (3.6),

    1. i didn't find a field to change the no of lanes for rx/tx. the first tab GT selection is GTX, the second tab protocol: start from scratch. Active Transceivers =8 showed at the bottom. I am not getting how to change the no  of lanes.

    2. apart from "jesd_link_parameters.h", i am getting error in "refdesign_rx_sv", out of range prefix 'rx_lane_data'[63:48]. i changed manually the parameters in that file.

    3. another error popped up q0_clk0_qtrefclk_pad_n_in does not exist.

    and i am afraid to endup somewhere, if keep on changing parameters manually,

  • 0 in reply to mohammad yasin chintapalli
    Prodigy 20 points

    Hi vijay,

    Thank u for u r support.

    1.I am now able to compile and generate the bit stream "jesd_link_parameters.h" and updating gtx transceiver wrapper.

    2. created a 1tx1rx  profile(no fb). [12410/12410] . Generating the LMK0408 clocks from Latte profile(122.88Mhz). After (in VIO) setting  the master reset to '1', qpll0 is locked status is '1'.

    This confirms the clock generation is fine.

    3.(in VIO) asserting the tx_sync_reset_vio=1, observed a clipped sine tone on tx_lane_data[0][63:0]. but observed no output from AFE7950_EVM.

    4.It is observed that the pin mapping in zc706/zcu102 for adc_sync,dac_sync , sysref are not connected to FMC pins of AFE7950 EVM.

    can u please help us in this regard how to proceed further.

    please find the log in latte

    Sysref Read as expected
    ###########Device DAC JESD-RX 0 Link Status###########
    Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
    CS State TX0: 0b00000000 . It is expected to be 0b00000010
    FS State TX0: 0b00000000 . It is expected to be 0b00000001
    Couldn't get the link up for device RX: 0; Alarms: 0x0
    ###################################
    ###########Device DAC JESD-RX 1 Link Status###########
    LOS Indicator for (Serdes Loss of signal) lane 0: 1
    Serdes-FIFO error for lane 0: 1
    Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
    CS State TX0: 0b00000000 . It is expected to be 0b00000010
    FS State TX0: 0b00000000 . It is expected to be 0b00000001
    Couldn't get the link up for device RX: 1; Alarms: 0x1100

  • 0 in reply to mohammad yasin chintapalli
    TI__Genius 10865 points

    Hi Yasin,

    Good to know you are able to generate bit stream and get q_pll lock.

    Regarding your question on GPIO mapping, I will reply offline via email. 

    Regards,

    Vijay