ADC12DJ3200: PLLalarm

Hi Kailyn,

I will check the config sequence but in the meantime can you ask following:

If they have cleared the alarm(section 7.3.9 alarm monitoring) and it still goes high?

Are they using the ADC12DJ3200EVM?

What are they using as the clock source?

Hi Miguel,

Thank you for you reply, after reset, the datasheet recommend to delay 750ns, is 100ms delay long? In addition, the customer used his own board, if he cleared the alarm, it is still high.  In addition, according to the above configuration, the FFT is normal except the a bit decrease with high frequency, but when he changed the sample rate, the FFT is also abnormal as below, could you please help to analyze?

Best regards

kailyn  

Hi Kailyn,

before we move forward to FFT plots, I want to make sure that the customer is getting the FG_DONE signal to go high. ADC needs to have calibrated properly in order to function correctly. Is the customer seeing the FG_DONE signal go high? What is the customer using for the clock source and it the voltage peak to peak spec from the datasheet met? Before the reset is set, can you make sure the customer is giving the ADC a CLK signal.

100ms is more than enough this is only for debug purposes.

Hello Miguel,

Thank you for your reply, the clock source is external clock to HMC7044, and then divider output to ADC, so  the customer provide the CLK before reset.

Now the FFT plot problem has been resolved, but the question is that the effective bit sometimes to decrease when using 1400Mhz to sample 400M,mode 14, 350MNCO. If he tried ten times, eight times the effective bit is 8, and there are two times the effective is back to 5. It seems like the floor noise caused the effective bit decrease. He is sure the floor noise doesn't come from power, so it there any other possibility to generate floor noise? 

Best regards

Kailyn