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ADS1278-EP: Performance of the device

Carlo
Expert 7715 points
Part Number: ADS1278-EP


Hi E2E,


Good day.


Based on the datasheet, the SCLK may be either in free-running or stop-clock operation between conversions. Other than power consumption, is there any difference in the device performance?
Also, the SPI format is limited to a CLK maximum input frequency of 27 MHz. What will happen if the SPI format is used above 27 MHz instead of Frame-Sync format?
It was also mentioned that as with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance. What will happen to the device if does not use a high-quality,low-jitter clock?
What implementation can be used for application demanding of frequency change about every 20ms to ensure same number of samples every cycle?


Regards,
Carlo

  • 0
    TI__Mastermind 23050 points

    Hi Carlo,

    There will not be any performance difference between free-running or stop-clock operation. The SPI format is limited to 27MHz and trying to operate faster than that is likely to result in insufficient setup and hold times and it is possible you will not be able to capture data.

    Jitter is going to degrade the performance of the device. How much depends on the frequency of the input signal. The classic formula for ideal SNR due to jitter is -20*log ( 2pi * Fin * Tjitter) + 10*log(OSR). Note the second term only applies for delta sigma converters that oversample the inputs. As long as the resulting SNR at your highest input frequency is a good bit better than the noise floor the ADC, the jitter will not have a significant impact. Keeping the jitter <50ps would guarantee that its noise contribution is negligible at even the highest input frequencies for this converter.

    Best,

    Zak