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Questions about DAC5681

Luis M Brugarolas
Intellectual 295 points

Other Parts Discussed in Thread: DAC5681

I have two questions relative to DAC5681.

a) Output compliance range is specified to AVDD +/-0.5 V and datasheet reports that exceeding the range may produce transistor breakdown and reduce device reliability. I am planning to bias output using active opamp termination with resistors biased to +5V as stated in sbaa150 example 3 for a simmilar current sink DAC. Does this requirement imposes restrictions to power supply sequencing or output compliance range may be ignored for short time?

b) In page 9 of datasheet is reported that CONFIG10 has to be configured accorging to DLL frequency. This is also mentioned in pag 33 about 'Recommended startup sequence', step 4. However in page 23, where CONFIG10 register is described, data does not match DLL frequency setting.

Best regards

Luis Miguel Brugarolas

  • 0
    TI__Expert 5820 points

    1) Luis, how long and how much beyond recommended range would the violation be? I would be inclined to use power sequencing but can confirm with designers if you have only minor violations that can be tolerated.

    2) CONFIG 10 values corresponding to DCLK frequency are given on page 9 of the datasheet. e.g. if DAC is running at 1000 MSPS, then DCLK is 500 MSPS (because data transfer is DDR fashion) and recommended CONFIG10 value is 0xC0.

    Regards

  • 0 in reply to Hamza Fraz
    Intellectual 295 points

    In reference to previos question and answer #2 just to point that the datasheet contains an error: pag 23 still describes the register with other fields.

    I have one more question in reference to digital interface timing. In page 9 of datasheet it is defined Tskew(A) and Tskew(B) but the presence of a negative figure for the later produces me certain doubts. Even more: figure 20 in page 28 describes these timing figures in a way which is different from my understanding.

    My guessing is the following:

    • Tskew(A) is the requirement for clock ahead of data: traditional hold time: how much data has to be stable after clock edge for data capture to be correct.
    • Tskew(B) is the requirement for data ahead of clock: traditional setup time: how much data has to be stable before clock edge for data capture to be correct. Being this figure negative just reflects that it refers to time before clock edge.

    Please, confirm if my guessings are correct.

    Best regards

    Luis Miguel

  • 0 in reply to Luis M Brugarolas
    TI__Expert 5820 points

    Luis

    DAC5681 expects DATACLK to be edge aligned to DATA and therefore it mentions the limits of tolerable skew around the data clock edge i.e. opposite of setup/hold times which define data valid window around the clock edge. The attached figure illustrates for DCLK of 400 MHz.

    I don't see any discrepancy on page 23 and page 9 values of CONFIG10. Page 9 gives you the recommended, PVT guaranteed values of CONFIG10 while page 23 lists all possible values.

    Regards

  • 0 in reply to Hamza Fraz
    Intellectual 295 points

    Frist question is clear now.

    In reference to CONFIG10 issue I missed the point. There is no contradiction at all.

    Best regards.