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DAC43401-Q1: Initial state of internal switches just after powering up and the switch state update timing

Takahiro Saito
Expert 5455 points
Part Number: DAC43401-Q1

Hi Team,

In the following figure, I can see 4 internal switches at VDD, REF, OUT and AGND.

My customer has a two questions regarding the internal switches.

1. Is it able to set the initial ON/OFF state for these switches by setting EEPROM? The Initial state means the state just after the POR. I understand the initial state of switches conncted to VDD and REF can be set by REF_EN bit at D1h. But, how about the switches at OUT and AGND?

2. Could you tell me the timing that the switch state is set after POR?

Regards,

Saito 

  • +1
    TI__Mastermind 41573 points

    Hi Saito-san,

    1. Yes, the VREF and VDD switch is based on the reference selection for the DAC. This can be set by the REF_EN bit in the GENERAL_CONFIG Register. The switch at OUT and AGND is determined by the device power down setting in the GENERAL_CONFIG Register. In high impedance power down, the switches are open. When it is powered down to 10-k, there is a 10k resistor to ground on the output pin which isn't shown in that block diagram.   The variable resistor R2 determines the reference gain setting. This is set by the DAC_SPAN bits in the GENERAL_CONFIG Register.    These can all be saved in the EEPROM
    2. After a POR the registers are loaded with the values saved in the EEPROM and the device state is valid after 30ms. 

    Best,

    Katlynne Jones

  • 0 in reply to Katlynne Jones
    TI__Expert 5455 points

    Hi Katlynne-san,

    Regarding question 2, does the DAC43401-Q1 keep the output state high-impedance until the device state is valid after POR?

    Regards,

    Saito

  • 0 in reply to Takahiro Saito
    TI__Mastermind 41573 points

    Hi Saito-san,

    I'd also like to double check this question with the design team. During the POR the default register values are loaded form the NVM, but I am unsure what the output state is while the registers are being loaded. Please allow a few days for their response. 

    Best,

    Katlynne 

  • +1 in reply to Katlynne Jones
    TI__Mastermind 41573 points

    Hi Saito-san, 

    I received confirmation that the DAC output state remains in hi-z mode after VDD is applied during the POR.

    Best,

    Katlynne Jones