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THS8200 vs THS8135

Roni Shoval
Prodigy 70 points

Other Parts Discussed in Thread: THS8135, THS8200

Hi,

 

I n the past I used the THS8135.

The THS8135 can recognize the video format timing and there is no need for any timing configuration.

I would like to know if the THS8200 the same mode of operation (no need for timing configuration)?

 

Best Reards

 

Roni

  • 0
    TI__Genius 16810 points
    Roni, Try the settings below for THS8200 Generic DAC operation. Output syncs will not be functinal with this setup. THS8200, REG 0x03=0xC1 THS8200, REG 0x1A=0x00 THS8200, REG,0x1C=0x70 THS8200, REG,0x38=0x07 THS8200, REG,0x82=0x1B
  • 0 in reply to Larry Taylor
    Prodigy 70 points
    Hi Larry, Thanks for your quick respond. This setup isn't good to me. I need to output video at YPbPr Output With Sync Signal Inserted on Y Channel Only. when I don't have the sync I can't see any picture. Is the THS8200 has any mode that could behave like the THS8135? Best regards Roni
  • 0 in reply to Roni Shoval
    TI__Genius 16810 points
    Roni, How did you generate the sync-on-Y using the THS8135? Did you use the /Blank, /Sync, and Sync-T control pins? The THS8200 cannot operate this way. Sync-on-Y can be generated directly from HS_IN, VS_IN, or digital embedded syncs, but the THS8200 must be programmed for various modes via I2C.
  • 0 in reply to Larry Taylor
    Prodigy 70 points

    Hi Larry,

     

    Thanks for your answer.

    I have another two questions:

    1. can you send me the registers setting for YCbCr 30 bit  480P and 480I?

    2. When I disconnect the input video and than connect it back i got green line all over the screen.

    I saw in the datasheet that i need to issue a software reset in order to synchronize the internal display timing generator to the

    input video source properly.

    However when i make a software reset (reg 0x03= 0x00, reg 0x03=0x01) the picture totally disappear from the screen.

    How can i solve this problem?

     

    Thanks in advance

    Best regards 

     

    Roni

  • 0 in reply to Roni Shoval
    TI__Genius 16810 points

    Roni,

    Do you want settings for use with separate HSYNC and VSYNC inputs to the THS8200?

    Your loss of picture could be related to FID polarity.  Two bits affect internal decode of filed start up.  A FID polarity issue can lead to THS8200 DTG start-up issues.

    For separate HSYNC, VSYNC, FID input setups:

    Set dtg1_field_flip bit in register 36h = 1

    Set dtg2_fid_pol bit in register 82h = 0

    Pull or dirve the THS8200 FID pin to logic low.

    The software reset toggle is a good way to check for proper FID decode and DTG startup

  • 0 in reply to Larry Taylor
    Prodigy 70 points

    Hi Larry,

     

    Yes, i would like the settings for separate HSYNC and VSYNC inputs.

     

    Regards

     

    Roni

  • 0 in reply to Roni Shoval
    TI__Genius 16810 points

    Roni,

    Try the settings below for 480i and 490p, 30-bit, with dicrete input syncs.  You may need to adjust the input sync polarities in REG82h to match your sync polarities.  The FID input must pulled are driven low for 480p, and toggling for 480i.  The CSM is used to map reduce bt601 YCbCr range to full-scale DAC output.

     

    //THS8200 480i
    WR_REG,THS8200,0x01,0x03,0x11 // chip_ctl
    // CSC setup not required if not used          
    WR_REG,THS8200,0x01,0x19,0x17 // csc_offset3  CSC bypassed      
    WR_REG,THS8200,0x01,0x1C,0x60 // dman_cntl  set to 30 bit input
    // composite sync amplitude control      
    WR_REG,THS8200,0x01,0x1D,0xFF // dtg_y_sync1        
    WR_REG,THS8200,0x01,0x1E,0x49 // dtg_y_sync2        
    WR_REG,THS8200,0x01,0x1F,0xFF // dtg_y_sync3        
    WR_REG,THS8200,0x01,0x20,0xFF // dtg_cbcr_sync1     
    WR_REG,THS8200,0x01,0x21,0xFF // dtg_cbcr_sync2     
    WR_REG,THS8200,0x01,0x22,0xFF // dtg_cbcr_sync3     
    WR_REG,THS8200,0x01,0x23,0x11 // dtg_y_sync_upper   
    WR_REG,THS8200,0x01,0x24,0x15 // dtg_cbcr_sync_upper
    // Horizontal timing parameters
    WR_REG,THS8200,0x01,0x25,0x3D // dtg_spec_a         
    WR_REG,THS8200,0x01,0x26,0x14 // dtg_spec_b         
    WR_REG,THS8200,0x01,0x27,0x1D // dtg_spec_c         
    WR_REG,THS8200,0x01,0x28,0x7C // dtg_spec_d         
    WR_REG,THS8200,0x01,0x29,0x00 // dtg_spec_d1        
    WR_REG,THS8200,0x01,0x2A,0x00 // dtg_spec_e         
    WR_REG,THS8200,0x01,0x2B,0x01 // dtg_spec_h_msb     
    WR_REG,THS8200,0x01,0x2C,0x6C // dtg_spec_h_lsb     
    WR_REG,THS8200,0x01,0x2D,0x01 // dtg_spec_i_msb     
    WR_REG,THS8200,0x01,0x2E,0x8D // dtg_spec_i_lsb     
    WR_REG,THS8200,0x01,0x2F,0x14 // dtg_spec_k_lsb     
    WR_REG,THS8200,0x01,0x30,0x00 // dtg_spec_k_msb     
    WR_REG,THS8200,0x01,0x31,0x0A // dtg_spec_k1        
    WR_REG,THS8200,0x01,0x32,0xAD // dtg_speg_g_lsb     
    WR_REG,THS8200,0x01,0x33,0x01 // dtg_speg_g_msb     
    WR_REG,THS8200,0x01,0x34,0x03 // dtg_total_pixel_msb
    WR_REG,THS8200,0x01,0x35,0x5A // dtg_total_pixel_lsb
    WR_REG,THS8200,0x01,0x36,0x80 // dtg_linecnt_msb    
    WR_REG,THS8200,0x01,0x37,0x04 // dtg_linecnt_lsb    
    WR_REG,THS8200,0x01,0x38,0x84 // dtg_mode           
    WR_REG,THS8200,0x01,0x39,0x21 // dtg_frame_field_msb
    WR_REG,THS8200,0x01,0x3A,0x0D // dtg_frame_size_lsb 
    WR_REG,THS8200,0x01,0x3B,0x07 // dtg_field_size_lsb

    // CSM set to map reduced YCbCr bt601 range to DAC Full-scale
    WR_REG,THS8200,0x01,0x41,0x40 // csm_clip_gy_low    
    WR_REG,THS8200,0x01,0x42,0x40 // csm_clip_bcb_low   
    WR_REG,THS8200,0x01,0x43,0x40 // csm_clip_rcr_low   
    WR_REG,THS8200,0x01,0x44,0xAC // csm_clip_gy_high   
    WR_REG,THS8200,0x01,0x45,0xAC // csm_clip_bcb_high  
    WR_REG,THS8200,0x01,0x46,0xAC // csm_clip_rcr_high  
    WR_REG,THS8200,0x01,0x47,0x40 // csm_shift_gy       
    WR_REG,THS8200,0x01,0x48,0x40 // csm_shift_bcb      
    WR_REG,THS8200,0x01,0x49,0x40 // csm_shift_rcr      
    WR_REG,THS8200,0x01,0x4A,0xDC // csm_mult_gy_msb    
    WR_REG,THS8200,0x01,0x4B,0x44 // csm_mult_bcb_rcr_msb
    WR_REG,THS8200,0x01,0x4C,0xAB // csm_mult_gy_lsb    
    WR_REG,THS8200,0x01,0x4D,0x91 // csm_mult_bcb_lsb   
    WR_REG,THS8200,0x01,0x4E,0x91 // csm_mult_rcr_lsb   
    WR_REG,THS8200,0x01,0x4F,0xF5 // csm_mode  

     WR_REG,THS8200,0x01,0x70,0x7C // dtg_hlength_lsb    
    WR_REG,THS8200,0x01,0x71,0x03 // dtg_hdly_msb       
    WR_REG,THS8200,0x01,0x72,0x31 // dtg_hdly_lsb       
    WR_REG,THS8200,0x01,0x73,0x12 // dtg_vlength_lsb    
    WR_REG,THS8200,0x01,0x74,0x00 // dtg_vdly_msb       
    WR_REG,THS8200,0x01,0x75,0x01 // dtg_vdly_lsb       
    WR_REG,THS8200,0x01,0x76,0x00 // dtg_vlength2_lsb   
    WR_REG,THS8200,0x01,0x77,0x00 // dtg_vdly2_msb      
    WR_REG,THS8200,0x01,0x78,0x00 // dtg_vdly2_lsb 
    // discrete input sync control  - use these to align picture 
    WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb  
    WR_REG,THS8200,0x01,0x7A,0x0F // dtg_hs_in_dly_lsb   use to adjust HSIN delay or horizontal position
    WR_REG,THS8200,0x01,0x7B,0x00 // dtg_vs_in_dly_msb  
    WR_REG,THS8200,0x01,0x7C,0x00 // dtg_vs_in_dly_lsb   use to adjust VSIN delay or vertical position
    WR_REG,THS8200,0x01,0x82,0x83 // pol_cntl  internal FID decode


    END_DATASET

    //THS8200 480p Generic Mode
    WR_REG,THS8200,0x01,0x03,0x11 // chip_ctl           
    WR_REG,THS8200,0x01,0x1C,0x60 // dman_cntl          
    WR_REG,THS8200,0x01,0x1D,0xFF // dtg_y_sync1        
    WR_REG,THS8200,0x01,0x1E,0x50 // dtg_y_sync2        
    WR_REG,THS8200,0x01,0x1F,0xFF // dtg_y_sync3        
    WR_REG,THS8200,0x01,0x20,0xFF // dtg_cbcr_sync1     
    WR_REG,THS8200,0x01,0x21,0xFF // dtg_cbcr_sync2     
    WR_REG,THS8200,0x01,0x22,0xFF // dtg_cbcr_sync3     
    WR_REG,THS8200,0x01,0x23,0x11 // dtg_y_sync_upper   
    WR_REG,THS8200,0x01,0x24,0x15 // dtg_cbcr_sync_upper
    WR_REG,THS8200,0x01,0x25,0x3D // dtg_spec_a         
    WR_REG,THS8200,0x01,0x26,0x10 // dtg_spec_b         
    WR_REG,THS8200,0x01,0x27,0x20 // dtg_spec_c         
    WR_REG,THS8200,0x01,0x28,0x7A // dtg_spec_d         
    WR_REG,THS8200,0x01,0x29,0x00 // dtg_spec_d1        
    WR_REG,THS8200,0x01,0x2A,0xC0 // dtg_spec_e         
    WR_REG,THS8200,0x01,0x2B,0x01 // dtg_spec_h_msb     
    WR_REG,THS8200,0x01,0x2C,0x90 // dtg_spec_h_lsb     
    WR_REG,THS8200,0x01,0x2D,0x03 // dtg_spec_i_msb     
    WR_REG,THS8200,0x01,0x2E,0x1B // dtg_spec_i_lsb     
    WR_REG,THS8200,0x01,0x2F,0x10 // dtg_spec_k_lsb     
    WR_REG,THS8200,0x01,0x30,0x00 // dtg_spec_k_msb     
    WR_REG,THS8200,0x01,0x31,0x00 // dtg_spec_k1        
    WR_REG,THS8200,0x01,0x32,0xAD // dtg_speg_g_lsb     
    WR_REG,THS8200,0x01,0x33,0x01 // dtg_speg_g_msb     
    WR_REG,THS8200,0x01,0x34,0x03 // dtg_total_pixel_msb
    WR_REG,THS8200,0x01,0x35,0x5A // dtg_total_pixel_lsb
    WR_REG,THS8200,0x01,0x36,0x80 // dtg_linecnt_msb    
    WR_REG,THS8200,0x01,0x37,0x08 // dtg_linecnt_lsb    
    WR_REG,THS8200,0x01,0x38,0x85 // dtg_mode           
    WR_REG,THS8200,0x01,0x39,0x27 // dtg_frame_field_msb
    WR_REG,THS8200,0x01,0x3A,0x0D // dtg_frame_size_lsb 
    WR_REG,THS8200,0x01,0x3B,0xFF // dtg_field_size_lsb 

    // CSM set to map reduced YCbCr range to DAC Full-scale
    WR_REG,THS8200,0x01,0x41,0x40 // csm_clip_gy_low    
    WR_REG,THS8200,0x01,0x42,0x40 // csm_clip_bcb_low   
    WR_REG,THS8200,0x01,0x43,0x40 // csm_clip_rcr_low   
    WR_REG,THS8200,0x01,0x44,0xAC // csm_clip_gy_high   
    WR_REG,THS8200,0x01,0x45,0xAC // csm_clip_bcb_high  
    WR_REG,THS8200,0x01,0x46,0xAC // csm_clip_rcr_high  
    WR_REG,THS8200,0x01,0x47,0x40 // csm_shift_gy       
    WR_REG,THS8200,0x01,0x48,0x40 // csm_shift_bcb      
    WR_REG,THS8200,0x01,0x49,0x40 // csm_shift_rcr      
    WR_REG,THS8200,0x01,0x4A,0xDC // csm_mult_gy_msb    
    WR_REG,THS8200,0x01,0x4B,0x44 // csm_mult_bcb_rcr_msb
    WR_REG,THS8200,0x01,0x4C,0xAB // csm_mult_gy_lsb    
    WR_REG,THS8200,0x01,0x4D,0x91 // csm_mult_bcb_lsb   
    WR_REG,THS8200,0x01,0x4E,0x91 // csm_mult_rcr_lsb   
    WR_REG,THS8200,0x01,0x4F,0xF5 // csm_mode    
     
          
    WR_REG,THS8200,0x01,0x70,0x40 // dtg_hlength_lsb    
    WR_REG,THS8200,0x01,0x71,0x03 // dtg_hdly_msb       
    WR_REG,THS8200,0x01,0x72,0x31 // dtg_hdly_lsb       
    WR_REG,THS8200,0x01,0x73,0x07 // dtg_vlength_lsb    
    WR_REG,THS8200,0x01,0x74,0x00 // dtg_vdly_msb       
    WR_REG,THS8200,0x01,0x75,0x07 // dtg_vdly_lsb       
    WR_REG,THS8200,0x01,0x76,0x00 // dtg_vlength2_lsb   
    WR_REG,THS8200,0x01,0x77,0xC7 // dtg_vdly2_msb      
    WR_REG,THS8200,0x01,0x78,0xFF // dtg_vdly2_lsb      
    WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb  
    WR_REG,THS8200,0x01,0x7A,0x0F // dtg_hs_in_dly_lsb   use to adjust horizontal alignment
    WR_REG,THS8200,0x01,0x7B,0x00 // dtg_vs_in_dly_msb  
    WR_REG,THS8200,0x01,0x7C,0x00 // dtg_vs_in_dly_lsb   use to adjust vetical alignment
    WR_REG,THS8200,0x01,0x82,0x03 // pol_cntl  exterrnal FID         

    END_DATASET

  • 0 in reply to Larry Taylor
    Prodigy 70 points

     

    Hi Larry,

    I'm using the setting for the 480i.

    My signal generator output CEA-861 video format 6 - 720(1440)x480i.

    On the TV I get bad picture.

    I attached the scope plot of the analog output AGY (pin 13).

    As you can see,the HSYNC rate is doubled then expected (31.25KHz instead of 15.734KHz).

     

     

    I will appreciate any suggestions.

     

    Best regards

     

    Roni

  • 0 in reply to Roni Shoval
    TI__Genius 16810 points

    Roni,

    The CEA-861 format is using a 2x pixel rate and line length.  Try using 2x settings for the dtg_spec horizontal timing registers an dtg_total pixels.

  • 0 in reply to Larry Taylor
    Prodigy 70 points

    Hi Larry,

     

    I changed the horizontal timing parameters and now I get correct timing.

    However, the vertical timing are not correct.

    As you can see in the figure below, the yellow signal is the Y output at VSYNC time.

    The blue signal is the input DE signal at VSYNC time.

    The VSYNC period on the Y output is much bigger than expected (should be the same as the DE).

    Because of that, the bottom part of the picture is black.

    the value of register dtg1_frame_size(10:0) is 525.

    the value of register dtg1_field_size(10:0) is 263.

    i tried to set register dtg1_mode(3:0) once to value 4 (ATSC mode 480I (SDTV 525 lines interlaced) [SDTV]) and once to value 9 (Generic mode for SDTV [SDTV]) and got the same output.

    When the value of dtg1_mode(3:0) was 9 i configured the following registers as well:

    wr 0x50 0x00

    wr 0x51 0x00

    wr 0x52 0x11

    wr 0x53 0x11

    wr 0x54 0x11

    wr 0x55 0x11

    wr 0x56 0x11

    wr 0x57 0x20

    wr 0x58 0x04

    wr 0x59 0x07

    wr 0x5A 0x0A

    wr 0x5B 0x14

    wr 0x5C 0x07

    wr 0x5D 0x08

    wr 0x5E 0x0A

    wr 0x5F 0x0B

    wr 0x60 0x0D

    wr 0x61 0x0E

    wr 0x62 0x10

    wr 0x63 0x11

    wr 0x64 0x1A

    wr 0x65 0x1B

    wr 0x66 0x0E

    wr 0x68 0xCD

    wr 0x69 0xC9

    wr 0x6A 0x07

    wr 0x6B 0xCF

    wr 0x6C 0xDE

    wr 0x6D 0xCB

    wr 0x6E 0x98

    wr 0x6F 0x00

    I read register dtg2_line_cnt(10:0) and its value is 525 and the value of register dtg2_ip_fmt is 1 (interlaced).

     

    Thanks for your help,

    Best Regards

    Roni

  • 0 in reply to Roni Shoval
    TI__Genius 16810 points

    Roni,

    Are you connecting a DE signal to the THS8200 FID input.  DE operastion is reserved for VESA graphics modes?  With interlaced video modes, the FID pin serves as a discrete FID input for field ID.  See REG 82h for more detail on FID operating modes.  If the THS8200 does properly detect FID, vertical position could vary, or there cold be no output. The software reset bit in REG 03h can be toggled to check FID decode consistency.  Vertcial position should remain constant when this bit is toggled.

    It it also possible that you have a vertical sync input alignment issue relative to active video.  You can use the dtg2_vs_in_dly registers to adjust vertical position.