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DAC80502: Can SYNC pin remain low between consecutive SPI writes.

Part Number: DAC80502

Hello,

I am trying to use the DACx0502 in my design. Reading the documentation, it is not clear whether SYNC pin can remain low between consecutive frames.

In particular, the use case I am thinking of is to set DAC1 and DAC2 data first, then followed by a write to the LDAC register, which is 3*24bit in total. Do I have to raise the SYNC pin high between each 24bit transfers or can I allow it to remain low between transfers? It is more convenient to write the software if they can remain low between consecutive SPI frames.

Thanks!