I have a board design with 4 identical ADC12DJ3200QML-SP devices driving 8 JESD204B SerDes Lanes each into a Xilinx KU060 FPGA.
Each JESD204B link has a PHY and the JESD protocol core.
At this time we have one link working properly and the other 3 do not work. The only difference I've noticed is when I read the OVR_CFG Register.
The working ADC reads x0F while the 3 failing ADC's all read xFF from the OVR_CFG register at address location x213.
The mapping of the upper nibble of OVR_CFG map to four RESERVED bits.
My Question is can TI provide anything specific about the values of these RESERVED bits?
In many chips Reserved signals and register bits are used for factory debug.
Thanks,
Mark Momcilovich