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ADC12DJ3200QML-SP: n/a

Part Number: ADC12DJ3200QML-SP

I have a board design with 4 identical ADC12DJ3200QML-SP devices driving 8 JESD204B SerDes Lanes each into a Xilinx KU060 FPGA.

Each JESD204B link has a PHY and the JESD protocol core.

At this time we have one link working properly and the other 3 do not work.  The only difference I've noticed is when I read the OVR_CFG Register.

The working ADC reads x0F while the 3 failing ADC's all read xFF from the OVR_CFG register at address location x213.

The mapping of the upper nibble of OVR_CFG map to four RESERVED bits.

My Question is can TI provide anything specific about the values of these RESERVED bits?

In many chips Reserved signals and register bits are used for factory debug.

Thanks,

Mark Momcilovich

  • Hi Mark,

    Looking into this and will get back to you with some guidance here.

    Regards,

    Rob

  • Hi Mark,

    Can you please confirm,  you can read the other register on the ADCs which are not working and let me know you are not reading 0xff on all the other registers?

    Also can send me the JMODE being used the clock rate and your programming sequence for the ADC.

    Regards,

    Neeraj

  • Hi Neeraj,  I'm able to read and write the internal register of all 4 ADC's.  We used a simple ramp test pattern and can see that pattern on the output of the GTH PHY and on the output of the Xilinx JESD core but only on our first ADC.  And, we read x0F from the OVR_CFG register at address x213 of this ADC.

    The other 3 ADC's DO NOT transmit a ramp test pattern and address x213 reads xFF.  It was the only difference I could find. I was thinking that since the RESERVED Bits (7:4) was form a register related to Over-range that perhaps the ADC's lock up when the RF input is over-range condition and can't transmit a ramp pattern.

    I will do some more thorough testing on Monday when I get back into the lab (after a design review) with more comprehensive results.

    For now we are using JMODE 0 and JESD204B subclass 0.

    Thanks,

    Mark

  • Hi Mark,

    Can you please send me the register write sequence you use to program the ADC?

    Regards,

    Neeraj