Can DAC8820 operate with transparent DAC register with LDAC permanently tied high but with the data latched into the input register as needed with the WR_N signal? Table 1 ("Function of Control Inputs") in the datasheet specifies that to load the input register both LDAC and WR_N should be low. But can input register be loaded on falling edge of WR_N while LDAC is high? Why isn't LDAC signal listed as "X" (do not care) instead of "0" in the second row in Table 1 in the datasheet (the row corresponding to loading the input register)? Thank you.