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ADS8586S: Reduce the sampling rate

Part Number: ADS8586S

Hi Team,

I understand from the other E2E thread that the sampling rate of a SAR ADC can be reduced. Our customer would like to know how to reduce the sampling rate of ADS8586S to 5-10 kSPS. It seems that the internal clock of the device is fixed and there is no option in the datasheet to select a lower sampling rate.

Regards,

Danilo

  • Hi Danilo,

    The actual sampling rate of ADS8586S is fsample = 1/tcyc, the cycle time (tcyc) is directly set by the signal of CONVSTA/B to the ADS8586S which is controlled by the customer's processor. For example, the tcyc should be 100us if 10ksps is expected by the customer. Please see the timing below, and the tcyc was highlighted in red. Let me know if you need any further support for this ADC. Thanks.

    Best regards,

    Dale

  • Hi Dale,

    Thank you very much for this information. It resolved our customer's inquiry.

    Regards,

    Danilo