ADS5409: Metastability protection for the SYNCp/n input pair, inside of the device

Part Number: ADS5409

ADS5409 has a SYNCp/n (LVDS differential pair) which forces the DDR output clock into a determinate state.

The datasheet (p.25) says that the SYNC signal is registered on the rising edge of CLKIN - the ADC sample clock.

Is there any metastability protection for this signal, within the device?  Namely, is it re-registered (once or more) to provide protection?

Or do I have to (pre)register the signal going into the SYNC inputs? (Not that easy...)

Any experience out there concerning this?

Thanks,

Noble Larson

Hardware design engineer

Axsun Technologies, Div. of Excelitas

Billerica, MA