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AMC3336EVM: DOUT does not appear give consistent readings

Bill Cunningham
Prodigy 50 points
Part Number: AMC3336EVM
Other Parts Discussed in Thread: AMC3336

I am testing with a AMC3336EVM to see how to read the value detected.  I am varying a 1.0V signal between INP and INN, but when I send the chip 16 clock cycles the value received on DOUT varies widely between read attempts for the same voltage.

My setup is that I am hooking INP and INN directly to the power supply that is supplying a 0.9V differential voltage.  I am powering the board at 3.3V from my Rapsberry Pi 4 and am using a GPIO pin on the same RPi 4 to provide the clock to the chip and then reading the DOUT on another RPi GPIO pin.  Ground is provided by the RPi and is the same for the VDD ground and for the CLK and DOUT.  I have CLKIN and DOUT hooked to an oscilloscope to see the DOUT signal with CLKIN. 

The EVM has been powered for a while before I try to clock in information from DOUT.  I leave the voltage unchanged and I send 16 clocks via CLKIN.  I expect that I should get the same bit pattern back from DOUT every time I apply the same CLKIN sequence, but the signal read back from DOUT changes, sometimes greatly.

For example, when I try to clock in a DOUT reading I might get something like the folllowing.

But when I try it again with the same exact voltage I would get something like the following.

My assumption is that the DOUT signals should be identical with the same voltage

I have varied the input voltage to 0.9V, 0V, and -0.7V with similar results.

Am I doing something wrong in how I'm trying to read this?  I would assuming bit-banging the CLKIN and then reading DOUT should work, am I wrong?

Please advise.

  • +1
    TI__Guru**** 181521 points

    Hi Bill,

    You won't see the behavior you are expecting with the AMC3336EVM.  The AMC3336 is not a traditional analog to digital converter, the output of this device is a digital bit-stream where the 1's density increases/decreases as the input voltage increases/decreases.  The behavior is described in section 7.3.4 and depicted in Figure 7-4.  If you were to capture 100 samples on DOUT with 1V applied to VINp (VINn=0V) you should see 90% of the output bits are logic 1.  If you repeat that capture, you would see the same 1's density, but it may not be exactly the same pattern.  You would need to use a digital filter to properly read the data encoded in the output bit-stream.