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LMK04828: Sync does not assert every time

RajK
Intellectual 740 points
Part Number: DAC37J82


Hello,

LMFS = 4211, K = 32, RBD = 19

Line rate = 8.1088Gbps, FPGA RefClk = 405.44MHz, FPGA Data clock = 202.72MHz, DAC sample clock = 810.88MHz

Sysref = 2.111666MHz (810.88/32*12), Sysref pulses = 8

Using these parameters, the initialization process has to be performed multiple times for the DAC to assert sync. Could you please provide recommendations on Sysref frequency and RBD value to guarantee sync assertion without having to perform initialization multiple times. Thank you

  • 0
    TI__Mastermind 28560 points

    Hello RajK,

    I apologize for the late response.

    Do you mean to de-assert sync?  Figure 37 of JESD204B standard shows for a TX device, after receiving a SYSREF, the SYNC~ transitions from low to high.  It also notes that Tx ILA beings on the first LMFC zero-crossing after SYNC~ is deasserted.  My understanding is the DAC is held in SYNC until the SYSREF comes.

    I think the RBD value will be a function of more than just clocking impact.  However for test purposes, you should be able to maximize to confirm all is working.

    The LMFC must be the same between all devices.  Can you confirm you are using
      * K=16 for the FPGA Ref Clock and K=8 for the FPGA Data Clock?  I imagine you are as your are getting your link to work sometimes.

    My recommendation would be to measure the time between the Device Clocks and the SYSREF and confirm it meets the timing requirement for the setup and hold of the SYSREF signal.

    The DAC has a 50 ps setup and hold requirement.  I don't know about your FPGA.  You could try adjust the phase relationship between SYSREF and device clock by using the SDCLKoutY_DDLY.  This is one of the simplest things to adjust as it's timing updates take effect immediately.

    Hope this helps.

    73,
    Timothy