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ADS8586S: Power consumption calculation

Vineeth N
Expert 1180 points
Part Number: ADS8586S
Other Parts Discussed in Thread: ADS8588S

Hi Team,

I developing a board for my project which uses ADS8586S. I am planning to sample the analog inputs at 10ksps and send the data via SPI to CC3220 at 250kHz. Is it possible to have different rates for input sampling and data throughput? Also I am sampling 6 channels simultaneously. So how do calculate the power requirement from the given electrical characteristics. 

It is given that Analog supply current 14.6mA at 250ksps. If I am calculating for worst case scenario I need to consider 19.8mA maximum current for my calculation right?. Since I am sampling simultaneously do I need to consider this 19.8mA for each channel? 

Same goes for Digital output for SPI communication since I am using three pins for my SPI, should I consider 0.3mA maximum current for 3 lines for my calculation?

My sample calculation is as follows.

AVDD = 5V

DVDD = 3.3V

IAVDD = 19.6mA

IDVDD = 0.3mA

sampling 6 channels simultaneously and SPI communication is working at 250kHz. Then,

Total Power consumed = ( 5*19.8mA*6 ) + ( 0.3*3.3 ) = 595mW 

Is this calculation correct?

Since I am using a AC/DC converter instead of  battery, I am calculating for maximum power requirement to choose my converter and LDO. Or should I need to account for static and power down conditions ?

Regards,

Vineeth

  • 0
    TI__Mastermind 46615 points

    Hi Vineeth,

    When the SCLK is 250kHz, the total time required for data transmission is 6*16*(1/250k)=384us, so the cycle time is 384us+3us=387 and the maximum sampling rate is 2.58ksps (other timing parameters are not considered). You can not get 10ksps sampling rate with your 250kHz SCLK even when two SDOs are used. To achieve 10ksps sampling rate, you have to increase your SCLK frequency from your controller.

    The dynamic (operational) analog supply current specification (maximum 19.8mA) should be used for your analog power consumption calculation. This is the specification for whole device and it's not a current specification per channel , so no need to multiply the number of channels. The 5V analog supply and the 3.3V digital power supply usually come from different supply sources, so the power consumption should be calculated separately. Also, you only need to consider the worse power consumption on AVDD and DVDD, so only a dynamic current should be considered.

    Regards,

    Dale

  • 0 in reply to Dale Li
    Expert 1180 points

    Hi Dale,

    Thank you for your reply. 

    Dale Li said:
    When the SCLK is 250kHz, the total time required for data transmission is 6*16*(1/250k)=384us, so the cycle time is 384us+3us=387 and the maximum sampling rate is 2.58ksps (other timing parameters are not considered). You can not get 10ksps sampling rate with your 250kHz SCLK even when two SDOs are used. To achieve 10ksps sampling rate, you have to increase your SCLK frequency from your controller.

    I didn't really got this point. As far as I understood the sampling rate is controlled by the CONVST signal. I thought I will sample at 10ksps using CONVST signals issued at 0.1ms intervals and sampled data from ADC will send out using SPI at serial clock provided by host at 250kHz. I might be wrong about this, if I am wrong please correct me.

    Also if you said is the case then, serial clock is actually determining the sampling speed and data transmission speed right?

    will ADS8586S store data after conversation till next conversion result. So that I can get the data whenever I want before the next conversion result?

    Regards,

    Vineeth

  • 0 in reply to Vineeth N
    TI__Mastermind 46615 points

    Hi Vineeth,

    It's true that the sampling rate is determined by the CONVST signal, however your SCLK is too slow so that your controller will not be able to retrieve the conversion data for all channels prior to next conversion start.

    The ADS8588S can shift out the data until next conversion start, however the new conversion data in next cycle will replace the previous conversion data. As I said, your controller will not be able to retrieve the conversion data for all channels prior to next conversion because your SCLK is too slow. My calculation in previous post showed this. You can

    • Increase your SCLK high enough to retrieve all data for achieving 10ksps sampling rate
    • OR reduce your sampling rate to 2.58ksps if you want to keep 250kHz SCLK frequency.

    I hope my explanation can help you understand.

    Regards,

    Dale

  • 0 in reply to Dale Li
    Expert 1180 points

    Hi Dale,

    I never thought about the thing that ADC cant keep the data for a long time. So to have a 10ksps rate I should go with 1 MHz serial clock. Which possible for this ADC I hope.

    Regards,

    Vineeth

  • +1 in reply to Vineeth N
    TI__Mastermind 46615 points

    Hi Vineeth,

    1MHz SCLK is close to the minimum clock requirement but it will be able to work for 10ksps sampling, 6*16*1us+3us+other timing parameters≈100us which is 10ksps. This is a calculation for one SDOA, also SDOB can be used if it's possible for you.

    Regards,

    Dale

  • 0 in reply to Dale Li
    Expert 1180 points

    Hi Dale,

    Thank you for your response. I will definitely increase my SCLK frequency as you said. I will be in touch with some other questions in future, I guess.

    Regards,

    Vineeth