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Hi Xiaoqiang,
The recommended input clock amplitude for a LVCMOS single-ended ac-coupled configuration is 1.5 V. (Please refer to page 11 on the datasheet here: https://www.ti.com/lit/ds/symlink/ads4222.pdf?ts=1634850418269&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FADS4222)
Regards, Amy
Thanks, I see. Most clock in market is 1.8V or 3.3V. Do you have any clock IC to recommend with low jitter? I need 2 channel output as to synchronize 2 ADS4222.
Hi Xiaoqiang,
There are plenty of clock buffers to choose from on the TI website.
if you let us know more about your needs, we can help down select.
Otherwise, please check out the following link that will get you started.
Regards,
Rob
1) one input = 50MHz
2) 2 LVDS output, output phase should be the same.
3) low jitter for ADS4222
Any recommendation?
Hi Xiaoqiang,
Are you in need of a buffer type solution, or a full clocking solution (with PLL, etc.)?
Can you let us know what is on the current EVM? Are there any clock solutions already?
Regards, Amy
Hi Xiaoqiang,
The CDCE72010 is on the EVM design and would be a suitable clock buffer for the ADS4222.
Regards,
Rob
Thanks, but I think CDCE72010 is over design for me. I just need two channel output and no need other features.