ADC12DL3200: Alignment of samples on the 4 LVDS buses

Hi Khee,

We are looking into this and will get back to you on Monday.

Regards,

Rob

Hi Rob,

Any update on this query?

Thanks,

Khee

Hi Neeraj,

Yes, I do have the LALIGNED bit set to '1'.

My other settings are:

- Select INA in single-channel mode

- LFRAME = 8 samples

- Device Sampling Clock = 6 GHz

What I've been seeing is that with LFRAME = 8 samples, occasionally in one or two LVDS buses, the first sample would be offset by 8 samples relative to the other buses.

Is SYSREF needed to reset the Strobe generator so that the samples in all LVDS buses are aligned? I read in one of your postings that SYSREF is not needed if you only have one ADC12DL3200 device in your design, so that was why I left out the SYSREF signal.

Regards,

Khee

Hi Khee,

No, SYSREF signal is not needed if you have one ADC12DL3200 device. 

Regards,

Neeraj 

Hi Neeraj,

Any suggestion as to why I'm getting the occasional misalignment of the samples?

Thanks,

Khee

Hi Khee,

Can you please share your register writes you are using to program the ADC? Have to tested with the test pattern mode?

Regards,

Neeraj

Hi Neeraj,

Here are my register writes to the ADC:

Register     Data

0x000         0xB0

(wait 5 msec)

0x200         0x00

0x061         0x00

0x060         0x01

0x030         0xFF

0x031         0xFF

0x032         0xFF

0x033         0xFF

0x062         0x02

0x201         0x07

0x202         0x08

0x204         0x02

0x206         0xFF

0x205         0x11

0x190         0x10

0x048         0x00

0x061         0x01

0x200         0x01

I'm using the default test pattern as input to my bitslip logic in the FPGA to align the bit patterns from all the LVDS bus lanes, and that seems to be working fine.

Regards,
Khee

Hi Khee,

if the test pattern is working as expected. when you see sample miss alignment? if you have a input signal applied to ADC and looking at normal data?

Regards,

Neeraj

Hi Neeraj,

Yes, I'm seeing the occasional sample misalignment when applying a sine wave to the ADC and looking at the captured samples.

Regards,

Khee

Hi Neeraj,

The issue remains when the sampling frequency is reduced by half.

Regards,

Khee

Hi Khee,

Here is what I think could be the cause of the issue. 

The FIFO has an issue on FPGA side.  FIFO is not implemented properly to align the LVDS data banks.

The reason every bus has it’s own strobe is to facilitate the process of aligning the data by using a FIFO. The frame size is 8 samples, so a shift of 8 samples is one frame. This type of shift is common if on of these situations occurs:

1. Too much skew between the buses/strobes arriving at the FIFO (caused by PCB or other sources)
2. The FIFO is implemented with a depth larger than 8 samples (per bus) and used a one-shot approach to reset the FIFO write pointer without accounting for skew properly.

Can you please provide following info. 

1. Do you use a FIFO to align the LVDS data from the four buses? If not, please explain how buses are being aligned.
2. If a FIFO is used, how deep is the FIFO?
3. If a FIFO is used, how is the write pointer for each bus initialized? Is the strobe signal for each bus used to initialize the pointer? If so, does every strobe pulse initialize the pointer (every 8 samples), or does only the “first” strobe pulse initialize the pointer? If only the “first” strobe pulse is used, how do you determine what the “first” pulse is? How do you ensure that all four FIFOs identify the “first” pulse properly to avoid an 8 sample shift?

Regards,

Neeraj

Hi Neeraj,

Please see my responses to your questions below:

        1. Do you use a FIFO to align the LVDS data from the four buses? If not, please explain how buses are being aligned.

            Yes. I use an IP provided by Xilinx to capture the LVDS data. There is an 8-sample FIFO within the IP.

        2. If a FIFO is used, how deep is the FIFO?

            See response to 1. above.

        3. If a FIFO is used, how is the write pointer for each bus initialized? Is the strobe signal for each bus used to initialize the pointer? If so, does every strobe pulse initialize the pointer (every 8 samples), or does only the “first” strobe pulse initialize the pointer? If only the “first” strobe pulse is used, how do you determine what the “first” pulse is? How do you ensure that all four FIFOs identify the “first” pulse properly to avoid an 8 sample shift?

            I have no control over the FIFO write pointer. That may be the cause of my problem.

Regards,

Khee

Hi Neeraj,

Can you please confirm that the SYSREF signal is not needed to align the ADC samples. Thanks.

Regards,

Khee