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TSC2007: About power up sequence of SDA & SCL pins

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Guru 21045 points
Part Number: TSC2007


Hi Team,

 

Our power up sequence is the following.

So, VDD and SDA & SCL are separated and 3.3V is applied to SDA & SCL first.

 

I guess that SDA & SCL are Digital input pins.

If yes, SDA & SCL will exceed ABSOLUTE MAXIMUM RATINGS.

 

Therefore, this sequence is not recommended.

Is my understanding correct?

And, could you please let us know if you have other concern?

 

[Sequence]

1.Powered up 3.3V of SDA & SCL

2.Powered up 3.3V of VDD

 

Regards,

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  • +1
    TI__Mastermind 23030 points

    generally you are correct that this sequence is not  recommended.

    However I2C is an open collector configuration and  the connection to the 3.3v is through a Pullup resistor. For example this can be 2.2k. This serves as a current limiter.

    IF SDA is High and Supply is zero then the 3.3V is returning 3.3/2k2 or 1.5ma into the chip pin. Choosing a

    high pullup value will reduce the current to the pin and if the time for which SDA/SCL are High and Supply is low is not too large, we might be able to tolerate  this condition. 

  • 0 in reply to Sanjay Dixit
    Guru 21045 points

    Hi Sanjay-san,

    Thank you for the information and advice.

    Regards,

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