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TSW14J57EVM: fpga compile

david sun77114
Expert 2162 points

Part Number: TSW14J57EVM
Other Parts Discussed in Thread: AFE58JD48

Dear Support, 

I have compiled TSWJ57 evaluation FPGA with Quartus PRO21.3, on Device 10AX115S2F45I1SG. if we are using the JESD204B RX only( from AFE58JD48). I want to figure out how to remove the TX related function and circuit. 

in the jest_top_cfg.sv, 

I changed 

//parameter gControllerType = "DAC_ADC" ;
parameter gControllerType = "ADC" ;

then when I compile, I will have this error message. 

Error: REFCLK port on the PLL is not properly connected on instance jesd204b_inst|jesd_top_qsys_0|jesd_top_qsys_0|u_jesd_top_inst|jesd_clk_rst_gen_0|JESD_A10_PLL.jesd_pll_inst|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst. This refclk port on the PLL must be connected.

I checked the ports are there, just don't understand why has this message, and failed compile.  how to remove the JEST TX related feature and logic? is removing TX logic save the resource and make the rest circuit runs faster?

for the provided package, it is very detailed and self sustained. don't laughing at me if I am too greedy. if I want do a very simple system level simulation, for example, send a data package from the jesd204b interface to the USB interface. is there a bus functional module I can use for FX3 USB interface and the jesd204b, and DDR4.  these module should be very popular, just don't know if they are shared for free. 

thanks,

David 

  • +1
    TI__Guru* 91947 points

    David,

    For system level simulation info, I would suggest contacting Intel since this is their IP and logic. We have nothing to offer regarding this. The firmware was also created by a third party vendor for TI, and they no longer are supporting us. The vendor did provide a design guide which I am attaching.

    Regards,

    Jim

    TSW14J57revE FW Architecture.docxTSW14J57revD & revE CER FW Architecture.docx

  • 0 in reply to jim s
    Expert 2162 points

    Hi Jim 

    How are you doing? I am so happy to see your response at this thread. I have read the document from TI, and play with the project on the Quartus. there is one of the develop document called TSW14J57 FW Register MAP. 

    for example, first line is "RX Capture Register" base address is "40_0000", offset value is "2_0000", and I also find the "Register/Signal Name (in FW) is DEC_CNTROL_REG_ADDR. in the "enc_data_gen_gz.sv"

    here are the definition of the address. 

    //Register offset for control registers
    `define ENC_CONTROL_REG_ADDR1 16'h8000
    //Regular BCM control register
    `define ENC_CONTROL_REG_ADDR2 16'h8001 //Just added the register alone, logic not implemented
    //BCM FW Pulse control Registers
    `define ENC_CONTROL_REG_ADDR3 16'h8004 //Enable register
    `define ENC_CONTROL_REG_ADDR4 16'h8005 //Pulse start index in terms of 512bit clock cycle
    `define ENC_CONTROL_REG_ADDR5 16'h8006 //Pulse width in terms of 512bit clock cycle

    I guess h8000 is 32 bit address, and offset h2_0000 is 8 bit address, so they are match.  but I don't know what the base address stand for. where to find the definition and which module use it to decode? could you please give me some hint? this is my email address if you think the information should not post to public. 

    I used to be a verification engineer, I will try to figure out use Intel tools to make some simulation. 

    Best Regards,

    David  

  • +1 in reply to david sun77114
    TI__Guru* 91947 points

    David,

    Attached is some more documents I found. Since our group does not support this device, I would suggest posting on the Medical  Imaging Data Converter Forum for more information.

    Regards,

    Jim 

    Design Documents.zip

  • 0 in reply to jim s
    Expert 2162 points

    Hi Jim 

    thank you very much for your kindly support, while I am reading the document and the source code, I may ask you the last question here.  

    in the document you send to me. in the TSW14J57 revE software flow.  I quote "If it is normal capture, set the capture start bit (Bit0 of the capture register) with required number of samples to RX_CAPTURE_REG (0x400000 + 0x20000). If it is triggered capture, " 

    and also there is a file called TSW14H57revE Fw register Map. 

    so far I haven't figure out the address space arrangement in the FPGA, where defined the Base address. if it is in the FPGA, while I reading more and more source code, I will find it sometime. but is the address space is the the FX3 USB chip firmware, without document and source code, it will hard for me to understand it. 

    hope you can give me some suggestion. I am very appreciate for all the files about TSW24J57. do you have similar document for TSW14J56, may be there are some information there that can help me. 

    Best Regards,

    David Sun

  • 0 in reply to jim s
    Expert 2162 points

    Hi Jim,

    Finally I figured out where address space defined. It is defined in the Intel Platform Designer. so you don't need to answer my question in last post, but if you could send me any TSW14J56 document, that will still be very helpful. 

    Thanks

    David

  • +1 in reply to david sun77114
    TI__Guru* 91947 points

    David,

    Files attached.

    Regards,

    Jim

    TSW14J56 documents.zip

  • 0 in reply to jim s
    Expert 2162 points

    Hi Jim

    Thank you very much, I notice in the package there is a zip file called FX3_FW, I think that is the firmware running in the USB3.0 chip which I couldn't find in the J57 package. 

    Have a nice day,

    David

  • +1 in reply to david sun77114
    TI__Guru* 91947 points

    David,

    Both EVM's use the same FX3 device so I think the firmware is the same.

    Regards,

    Jim

  • 0 in reply to jim s
    Expert 2162 points

    Hi Jim

    we are going to port TSW14J57 to Intel Arria 10 GX board, and use it with 4 AFE58jd48. is there any paper or example to integrated multiple ADC like AFE58jd48 and use JESD to upload the data. I remember I have read some document at TI, but now I can remember what is the document and couldn't find it anymore. I need know a little more detail how to bundle two or more device to JESD. 

    Thanks,

    David 

  • 0 in reply to david sun77114
    TI__Mastermind 45670 points

    Hi Dave,

    Sorry for the delay, Jim has been out. I will find out from the team if there is a paper or document to forward.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Expert 2162 points

    Hi Rob, 

    Nice to know new friends at the TI forum. while develop new product there are always so many questions to ask, and there are so little resource to rely on.  I posted quit a few question on the Intel forum because they are FPGA related. but from the system level design question, still need TI support. I believe I will have a lot of questions once you are linked. 

    Regards,

    David Sun

  • 0 in reply to Rob Reeder
    Expert 2162 points

    Hi Rob, 

    I can ask my question in a more straight forward way. while we are linking 4 AFE58JD48 to TSW14J57. I need some help to configure the LFM. 

    the TSW14J57 can support 16 directly. so I think L can be set to 16. 

    if the AFE sample rate is 100Mhz.  Lane = 4. I have no idea how to set the M, F, and other corelated parameters. 

    I hope someone really familiar with AFE58JD48 give me some suggestion. 

    Best Regards,

    David