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Hello Ao,
We would like to take this conversation offline since the device AFE5832 is covered under selective disclosure.
Can you please reach out to support_us_afe_tx@list.ti.com along with a reference to this e2e post?
Hi Praveen Aroul,
Ao helped me to send this question, I add some more
i give the adc clock 80Mhz. set 12bit, x1 rate.
1) I serdes FCLK by DCLK ,the value 111111111111000000000000 is very stable under sync mode. But not at ramp mode.
at sync mode the fclk stably:
at ramp mode the fclk instably:
2) My power up sequence shows by Ao , Could you help me to check it?
3) i tried two ways to serdes lvds data as below:
(1) i use sync test pattern 111111000000 , then set delay time in and bitslip the data line . after that, it can match the value well , but the data is wrong by change to ramp mode.
(2) i serdes FCLK, bitslip FCLK and DATA to let FCLK match 111111111111000000000000. but the data not the same in the same chip.
4) what the right power sequence?
i look forward to your reply. thanks.
and what the situation to use the tx_trig signal ? I only use it during power sequence.
Hello Lucas,
Can you send the queries to the mailing list support_us_afe_tx@list.ti.com?
Hi Ao,
Since we are supporting this request over mail due to NDA restrictions, I am closing this thread and we can continue the discussion over mail.
Thanks & regards,
Abhishek