ADC12DJ5200RF: ADC Overrange Detection Clarification

Hi Steve,

Steve Widener said:

1. Please confirm that the ORA0, ORA1 pins are driven high even if one sample is above the OVR_T0, OVR_T1 threshold levels

Yes 

Steve Widener said:

2. Please confirm that if ORA0, ORA1 are driven high, that they stay high for the number of DEVCLK cycles set by OVR_N in Table 7-3

     ---- for instance, the ORA0, 1 pin essentially pulse stretches the configured number of DEVCLK cycles triggered from the last ORA0,1  event

Yes

Steve Widener said:

. If the ADC12DJ5200RF is operated in single channel mode at 5.2Gsps, is DEVCLK for the purposes of the above mentioned stretching time = 10.4GHz (per table 7-5)?

     ---- If this were the case, and let's say OVR_N = 7, then a single overrange sample on CHA would yield an ORA0,1 pulse length of 1024 * (1/10.4G) = 98.46nsec

     ---- or is it the case that a single overrange sample on CHA would yield an ORA0,1 pulse length of 1024 * (1/5.2G) = 196.9nsec

No pulse stretching is based on Dev clk frequency(5.2GHz) and not the sampling rate. 

  This is the correct the case that a single overrange sample on CHA would yield an ORA0,1 pulse length of 1024 * (1/5.2G) = 196.9nsec

Steve Widener said:

4. Let's say we are in JMODE 24 (CS=1, decimate by 8, single channel) sampling DES at 5.2GHz input clock. If we get an overrange, do the ORA0,1 bits still set AND the LSB of the of the Channel A samples is also set?

Yes both ORA0 pin go high as well as OVERRANGE the LSB of CHA is also set. 

Steve Widener said:

For the situation in "3&4" above, what is meant by the MONITORING PERIOD" as called out in Table 7-4? 

     --- Does this mean that when an overrange is detected, the decimated transport data LSB will "stretch" for 2^7 = 128 ADC samples? (Is that FCLK = 5.2GHZ or DEVCLK at 10.4GHz)?

Monitoring Period means amount of time for which the pulse will be stretched. It is based dev clk frequency 5.2GHz.

Regards,
Neeraj