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ADC12DJ2700: FG calibration failure

Gil Hershman71
Intellectual 590 points
Part Number: ADC12DJ2700
Other Parts Discussed in Thread: LMK04828, LMX2592, LMH5401, ADC12DJ5200RF

ello,

We have an issue with the Foreground Calibration in the ADC12DJ2700.

Normally, meaning for JMODE_0, JMODE_2, foreground calibration passes.

Also, for JMODE_16 with sample clocks of ~2450 and higher, foreground calibration passes.

For JMODE_16, for lower sample clocks, mainly at ~2400MHz and lower, it fails.

 

Usually, FG_DONE bit polling took up to 400msec until successful FG calibration was detected.

We tried extending the time to few seconds what with no use. The failure is still there.

 

What can affect FG calibration failure in our case?

How should we debug this?

 

Background information:

In our design, the LMK04828 is used as the clock distribution device for the JESD204B DEVCLK and SYSREF,
which feeds a Xilinx FPGA (JESD204B receiver) and a LMX2592, which supplies the ADC12DJ2700 sample clock.

The system analog input goes to a LMH5401 diff opamp (SE input to DIFF outputs), which feeds the ADC12DJ2700.

 Attached find the ADC register dump for JMODE_16, 2700MHz (FG calibration pass) and JMODE_16, 2200MHz (FG calibration fail).

Fullscreen AdcRegisterDump.txt Download 
=== ADC 2700 MHZ, Two Channel, X16

======================================================================
ADC-12-DJ-2700 Registers 
======================================================================
0x000 - CONFIG_A:           0x30
0x002 - DEVICE_CONFIG:      0x00
0x003 - CHIP_TYPE:          0x03
0x004 - CHIP_ID_A:          0x20
0x005 - CHIP_ID_B:          0x00
0x006 - CHIP_VERSION:       0x0a
0x00C - VENDOR_ID_A:        0x51
0x00D - VENDOR_ID_B:        0x04
0x010 - USR0:               0x00
0x029 - CLK_CTRL_0:         0x60
0x02A - CLK_CTRL_1:         0x20
0x02C - SYSREF_POS[7:0]:    0x8d
0x02D - SYSREF_POS[15:8]:   0x31
0x02E - SYSREF_POS[23:16]:  0xc6
0x030 - FS_RANGE_A[7:0]:    0xff
0x031 - FS_RANGE_A[15:8]:   0xff
0x032 - FS_RANGE_B[7:0]:    0xff
0x033 - FS_RANGE_B[15:8]:   0xff
0x038 - BG_BYPASS:          0x00
0x03B - TMSTP_CTRL:         0x00
0x048 - SER_PE:             0x07
0x060 - INPUT_MUX:          0x01
0x061 - CAL_EN:             0x01
0x062 - CAL_CFG0:           0x05
0x06A - CAL_STATUS:         0x0b
0x06B - CAL_PIN_CFG:        0x00
0x06C - CAL_SOFT_TRIG:      0x01
0x06E - CAL_LP:             0x88
0x070 - CAL_DATA_EN:        0x00
0x071 - CAL_DATA:           0x00
0x07A - GAIN_TRIM_A:        0xb3
0x07B - GAIN_TRIM_B:        0xab
0x07C - BG_TRIM:            0x0b
0x07E - RTRIM_A:            0xa7
0x07F - RTRIM_B:            0xaf
0x080 - TADJ_A_FG90:        0xbf
0x081 - TADJ_B_F_G0:        0x80
0x082 - TADJ_A_BG90:        0xb4
0x083 - TADJ_C_BG0:         0x98
0x084 - TADJ_C_BG90:        0xe0
0x085 - TADJ_B_BG0:         0x80
0x086 - TADJ_A:             0x61
0x087 - TADJ_CA:            0x92
0x088 - TADJ_CB:            0x97
0x089 - TADJ_B:             0x80
0x08A - OADJ_A_INA[7:0]:    0xfc
0x08B - OADJ_A_INA[15:8]:   0x07
0x08C - OADJ_A_INB[7:0]:    0x85
0x08D - OADJ_A_INA[15:8]:   0x07
0x08E - OADJ_C_INA[7:0]:    0x8a
0x08F - OADJ_C_INA[15:8]:   0x07
0x090 - OADJ_C_INB[7:0]     0x6e
0x091 - OADJ_C_INA[15:8]:   0x07
0x092 - OADJ_B_INA[7:0]:    0x59
0x093 - OADJ_B_INA[15:8]:   0x07
0x094 - OADJ_B_INB[7:0]:    0x85
0x095 - OADJ_B_INB[15:8]:   0x07
0x097 - OSFILT0:            0x00
0x098 - OSFILT1:            0x33
0x102 - B0_TIME_0:          0x7a
0x103 - B0_TIME_90:         0x86
0x112 - B1_TIME_0:          0x80
0x113 - B1_TIME_90:         0x80
0x122 - B2_TIME_0:          0x76
0x123 - B2_TIME_90:         0x81
0x132 - B3_TIME_0:          0x80
0x133 - B3_TIME_90:         0x80
0x142 - B4_TIME_0:          0x83
0x143 - B4_TIME_90:         0x80
0x152 - B5_TIME_0:          0x80
0x153 - B5_TIME_90:         0x80
0x160 - ENC_LSB:            0x00
0x200 - JESD_EN:            0x01
0x201 - JMODE:              0x10
0x202 - KM1:                0x05
0x203 - JSYNC_N:            0x01
0x204 - JCTRL:              0x01
0x205 - JTEST:              0x00
0x206 - DID:                0x00
0x207 - FCHAR:              0x00
0x208 - JESD_STATUS:        0x7c
0x209 - PD_CH:              0x00
0x20A - JEXTRA_A:           0x00
0x20B - JEXTRA_B:           0x00
0x210 - DDC_CFG:            0x00
0x211 - OVR_T0:             0xf2
0x212 - OVR_T1:             0xab
0x213 - OVR_CFG:            0x07
0x214 - CMODE:              0x00
0x215 - CSEL:               0x00
0x216 - DIG_BIND:           0x00
0x217 - NCO_RDIV[7:0]:      0x00
0x218 - NCO_RDIV[15:8]:     0x00
0x219 - NCO_SYNC:           0x01
0x220 - FREQA0[7:0]:        0xb4
0x221 - FREQA0[15:8]:       0x97
0x222 - FREQA0[23:16]:      0xd0
0x223 - FREQA0[31;24]:      0x5e
0x224 - PHASEA0[7:0]:       0x00
0x225 - PHASEA0[15:8]:      0x00
0x228 - FREQA1[7:0]:        0x00
0x229 - FREQA1[15:8]:       0x00
0x22A - FREQA1[23:16]:      0x00
0x22B - FREQA1[31;24]:      0xc0
0x22C - PHASEA1[7:0]:       0x00
0x22D - PHASEA1[15:8]:      0x00
0x230 - FREQA2[7:0]:        0x00
0x231 - FREQA2[15:8]:       0x00
0x232 - FREQA2[23:16]:      0x00
0x233 - FREQA2[31;24]:      0xc0
0x234 - PHASEA2[7:0]:       0x00
0x235 - PHASEA2[15:8]:      0x00
0x238 - FREQA3[7:0]:        0x00
0x239 - FREQA3[15:8]:       0x00
0x23A - FREQA3[23:16]:      0x00
0x23B - FREQA3[31;24]:      0xc0
0x23C - PHASEA3[7:0]:       0x00
0x23D - PHASEA3[15:8]:      0x00
0x240 - FREQB0[7:0]:        0xb4
0x241 - FREQB0[15:8]:       0x97
0x242 - FREQB0[23:16]:      0xd0
0x243 - FREQB0[31;24]:      0x5e
0x244 - PHASEB0[7:0]:       0x00
0x245 - PHASEB0[15:8]:      0x00
0x248 - FREQB1[7:0]:        0x00
0x249 - FREQB1[15:8]:       0x00
0x24A - FREQB1[23:16]:      0x00
0x24B - FREQB1[31;24]:      0xc0
0x24C - PHASEB1[7:0]:       0x00
0x24D - PHASEB1[15:8]:      0x00
0x250 - FREQB2[7:0]:        0x00
0x251 - FREQB2[15:8]:       0x00
0x252 - FREQB2[23:16]:      0x00
0x253 - FREQB2[31;24]:      0xc0
0x254 - PHASEB2[7:0]:       0x00
0x255 - PHASEB2[15:8]:      0x00
0x258 - FREQB3[7:0]:        0x00
0x259 - FREQB3[15:8]:       0x00
0x25A - FREQB3[23:16]:      0x00
0x25B - FREQB3[31;24]:      0xc0
0x25C - PHASEB3[7:0]:       0x00
0x25D - PHASEB3[15:8]:      0x00
0x297 - SPIN_ID:            0x01
0x2B0 - SRC_EN:             0x01
0x2B1 - SRC_CFG:            0x0b
0x2B2 - SRC_TAD[7:0]:       0x0d
0x2B3 - SRC_TAD[15:8]:      0x93
0x2B4 - SRC_TAD[23:16]:     0x02
0x2B5 - TAD[7:0]:           0x00
0x2B6 - TAD[15:8]:          0x00
0x2B7 - TAD[23:16]:         0x00
0x2B8 - TAD_RAMP:           0x00
0x2C0 - ALARM:              0x01
0x2C1 - ALM_STATUS:         0x0a
0x2C2 - ALM_MASK:           0x00


====== ADC 2200MHz  , TWO Channel , X16
======================================================================
ADC-12-DJ-2700 Registers 
======================================================================
0x000 - CONFIG_A:           0x30
0x002 - DEVICE_CONFIG:      0x00
0x003 - CHIP_TYPE:          0x03
0x004 - CHIP_ID_A:          0x20
0x005 - CHIP_ID_B:          0x00
0x006 - CHIP_VERSION:       0x0a
0x00C - VENDOR_ID_A:        0x51
0x00D - VENDOR_ID_B:        0x04
0x010 - USR0:               0x00
0x029 - CLK_CTRL_0:         0x60
0x02A - CLK_CTRL_1:         0x20
0x02C - SYSREF_POS[7:0]:    0x31
0x02D - SYSREF_POS[15:8]:   0x0c
0x02E - SYSREF_POS[23:16]:  0x83
0x030 - FS_RANGE_A[7:0]:    0xff
0x031 - FS_RANGE_A[15:8]:   0xff
0x032 - FS_RANGE_B[7:0]:    0xff
0x033 - FS_RANGE_B[15:8]:   0xff
0x038 - BG_BYPASS:          0x00
0x03B - TMSTP_CTRL:         0x00
0x048 - SER_PE:             0x07
0x060 - INPUT_MUX:          0x01
0x061 - CAL_EN:             0x01
0x062 - CAL_CFG0:           0x05
0x06A - CAL_STATUS:         0x0c
0x06B - CAL_PIN_CFG:        0x00
0x06C - CAL_SOFT_TRIG:      0x01
0x06E - CAL_LP:             0x88
0x070 - CAL_DATA_EN:        0x00
0x071 - CAL_DATA:           0x00
0x07A - GAIN_TRIM_A:        0xc9
0x07B - GAIN_TRIM_B:        0x4b
0x07C - BG_TRIM:            0x0c
0x07E - RTRIM_A:            0xac
0x07F - RTRIM_B:            0x6b
0x080 - TADJ_A_FG90:        0x57
0x081 - TADJ_B_F_G0:        0xc0
0x082 - TADJ_A_BG90:        0xbf
0x083 - TADJ_C_BG0:         0x2b
0x084 - TADJ_C_BG90:        0x3c
0x085 - TADJ_B_BG0:         0xc5
0x086 - TADJ_A:             0x40
0x087 - TADJ_CA:            0x00
0x088 - TADJ_CB:            0x80
0x089 - TADJ_B:             0xd3
0x08A - OADJ_A_INA[7:0]:    0x3d
0x08B - OADJ_A_INA[15:8]:   0x03
0x08C - OADJ_A_INB[7:0]:    0x04
0x08D - OADJ_A_INA[15:8]:   0x04
0x08E - OADJ_C_INA[7:0]:    0x40
0x08F - OADJ_C_INA[15:8]:   0x0b
0x090 - OADJ_C_INB[7:0]     0x0b
0x091 - OADJ_C_INA[15:8]:   0x04
0x092 - OADJ_B_INA[7:0]:    0x40
0x093 - OADJ_B_INA[15:8]:   0x00
0x094 - OADJ_B_INB[7:0]:    0x1c
0x095 - OADJ_B_INB[15:8]:   0x04
0x097 - OSFILT0:            0x00
0x098 - OSFILT1:            0x33
0x102 - B0_TIME_0:          0x40
0x103 - B0_TIME_90:         0x40
0x112 - B1_TIME_0:          0x40
0x113 - B1_TIME_90:         0x7f
0x122 - B2_TIME_0:          0xce
0x123 - B2_TIME_90:         0x07
0x132 - B3_TIME_0:          0x10
0x133 - B3_TIME_90:         0x40
0x142 - B4_TIME_0:          0x40
0x143 - B4_TIME_90:         0x14
0x152 - B5_TIME_0:          0x08
0x153 - B5_TIME_90:         0x04
0x160 - ENC_LSB:            0x00
0x200 - JESD_EN:            0x01
0x201 - JMODE:              0x10
0x202 - KM1:                0x05
0x203 - JSYNC_N:            0x01
0x204 - JCTRL:              0x01
0x205 - JTEST:              0x00
0x206 - DID:                0x00
0x207 - FCHAR:              0x00
0x208 - JESD_STATUS:        0x00
0x209 - PD_CH:              0x00
0x20A - JEXTRA_A:           0x00
0x20B - JEXTRA_B:           0x00
0x210 - DDC_CFG:            0x00
0x211 - OVR_T0:             0xf2
0x212 - OVR_T1:             0xab
0x213 - OVR_CFG:            0x07
0x214 - CMODE:              0x00
0x215 - CSEL:               0x00
0x216 - DIG_BIND:           0x00
0x217 - NCO_RDIV[7:0]:      0x00
0x218 - NCO_RDIV[15:8]:     0x00
0x219 - NCO_SYNC:           0x00
0x220 - FREQA0[7:0]:        0x45
0x221 - FREQA0[15:8]:       0x17
0x222 - FREQA0[23:16]:      0x5d
0x223 - FREQA0[31;24]:      0x74
0x224 - PHASEA0[7:0]:       0x00
0x225 - PHASEA0[15:8]:      0x00
0x228 - FREQA1[7:0]:        0x00
0x229 - FREQA1[15:8]:       0x00
0x22A - FREQA1[23:16]:      0x00
0x22B - FREQA1[31;24]:      0xc0
0x22C - PHASEA1[7:0]:       0x00
0x22D - PHASEA1[15:8]:      0x00
0x230 - FREQA2[7:0]:        0x00
0x231 - FREQA2[15:8]:       0x00
0x232 - FREQA2[23:16]:      0x00
0x233 - FREQA2[31;24]:      0xc0
0x234 - PHASEA2[7:0]:       0x00
0x235 - PHASEA2[15:8]:      0x00
0x238 - FREQA3[7:0]:        0x00
0x239 - FREQA3[15:8]:       0x00
0x23A - FREQA3[23:16]:      0x00
0x23B - FREQA3[31;24]:      0xc0
0x23C - PHASEA3[7:0]:       0x00
0x23D - PHASEA3[15:8]:      0x00
0x240 - FREQB0[7:0]:        0x45
0x241 - FREQB0[15:8]:       0x17
0x242 - FREQB0[23:16]:      0x5d
0x243 - FREQB0[31;24]:      0x74
0x244 - PHASEB0[7:0]:       0x00
0x245 - PHASEB0[15:8]:      0x00
0x248 - FREQB1[7:0]:        0x00
0x249 - FREQB1[15:8]:       0x00
0x24A - FREQB1[23:16]:      0x00
0x24B - FREQB1[31;24]:      0xc0
0x24C - PHASEB1[7:0]:       0x00
0x24D - PHASEB1[15:8]:      0x00
0x250 - FREQB2[7:0]:        0x00
0x251 - FREQB2[15:8]:       0x00
0x252 - FREQB2[23:16]:      0x00
0x253 - FREQB2[31;24]:      0xc0
0x254 - PHASEB2[7:0]:       0x00
0x255 - PHASEB2[15:8]:      0x00
0x258 - FREQB3[7:0]:        0x00
0x259 - FREQB3[15:8]:       0x00
0x25A - FREQB3[23:16]:      0x00
0x25B - FREQB3[31;24]:      0xc0
0x25C - PHASEB3[7:0]:       0x00
0x25D - PHASEB3[15:8]:      0x00
0x297 - SPIN_ID:            0x00
0x2B0 - SRC_EN:             0x01
0x2B1 - SRC_CFG:            0x0b
0x2B2 - SRC_TAD[7:0]:       0x00
0x2B3 - SRC_TAD[15:8]:      0x00
0x2B4 - SRC_TAD[23:16]:     0x03
0x2B5 - TAD[7:0]:           0x00
0x2B6 - TAD[15:8]:          0x00
0x2B7 - TAD[23:16]:         0x00
0x2B8 - TAD_RAMP:           0x00
0x2C0 - ALARM:              0x00
0x2C1 - ALM_STATUS:         0x1f
0x2C2 - ALM_MASK:           0x1f

Thank you,

Gil

  • 0
    TI__Mastermind 20541 points

    Hi Gil,

    Can you please confirm you have seen this issue on multiple devices? Also can you please share register write sequence you have you use to program the ADC?

    Regards,

    Neeraj

  • 0 in reply to Neeraj Gill
    Intellectual 590 points

    Hi Neeraj,

    Yes. We have seen this in multiple systems.

    The writing sequence for JMODE_0 and JMODE_2 produces a successful FG calibration.

    In JMODE_16, in a specific sampling frequency range (~2400MHz and lower), the FG calibration fails.

    In JMODE_16 with sample clocks of ~2450 and higher, foreground calibration passes.

    The writing sequence is as follows:

    R000.SOFT_RESET = 1

    SLEEP 1us

    R2C2                                       = 0x1F

    R200.JESD_EN                      = 0

    R061.CAL_EN                       = 0

    R029.SYSREF_RECV_EN   = 1

    R029.SYSREF_PROC_EN   = 1

    R03B. TMSTP_RECV_EN    = markingEn ;  “1” enable ADC marking , “0” disable ADC marking

    R03B. TMSTP_LVPECL_EN = markingEn

    R160.TIMESTAMP_EN        = markingEn

    R201.JMOD                           = JMOD ;  0/2/16

    R202.KM1                              = 0x5

    R204.SYNC_SEL                  = 0

    R204.SCR                               = 1

    R204.SFORMAT                   = 0

    R030.FS_RANGE_A[15:8]   = FS_A[15:8] ; 0x2000 500mVpp , 0xA000 800mVpp , 0xFFFF 1000mVpp

    R031.FS_RANGE_A[7:0]     = FS_A[7:0]

    R032.FS_RANGE_B[15:8]    = FS_B[15:8]

    R033.FS_RANGE_B[7:0]      = FS_B[7:0]

    R216.DIG_BIND_A              = 0

    R216.DIG_BIND_B              = ~ adcChanDigtalBindEn ; “1” DDC1 and DDC2 are sourced from channel1

    R219.NCO_SYNC_ILA        = 0

    R219.NCO_SYNC_NEXT    = 0

    R220                                       = FREQA[31:24] ; frequency for DDC1 NCO

    R221                                       = FREQA[23:16]

    R222                                       = FREQA[15:8]

    R223                                       = FREQA[7:0]

    R240                                       = FREQB[31:24] ; frequency for DDC2 NCO

    R241                                       = FREQB[23:16]

    R242                                       = FREQB[15:8]

    R243                                       = FREQB[7:0]

    R225                                       = PHASEA0[15:8] ; phase for DDC1 NCO

    R224                                       = PHASEA0[7:0]

    R245                                       = PHASEB0[15:8] ; phase for DDC2 NCO

    R244                                       = PHASEB0[7:0]

    R048.SER_PE                        = 0x7

    R062.CAL_CFG                    = 0x5

    R029.SYSREF_SEL  = 0

    R2B0.SRC_EN          = 0

    R2B1.SRC_AVG       = 2

    R2B1.SRC_HDUR    = 3

    R2B0.SRC_EN          = 1

    Wait for R2B4.SRC_DONE = 1

    R061.CAL_EN                       = 1

    R200.JESD_EN                      = 1

    R06C.CAL_SOFT_TRIG      = 0

    R06C.CAL_SOFT_TRIG      = 1

    Wait for R06A.FG_DONE    = 1

    R2C2                                       = 0x0

    In the first post, you can find the ADC12DJ2700 register values when FG calibration fails and when it passes.

    Can you describe the possible causes for a FG calibration to fail?

    Thank you

    Gil

  • 0 in reply to Gil Hershman71
    TI__Mastermind 20541 points

    Hi Gil,

    One though is that the values from the fuse ROM are not getting loaded properly to the ADC. In your register write sequence for the second step can you try the following two things.

    1. Increase the delay to from 1us to 100ms. Or instead of delay poll the bit '0' of register address 0x270. When the fuse is done loading it will read 1. So wait for bit 0 to read 1 and then proceed with further register writes.

    Regards,

    Neeraj

  • 0 in reply to Neeraj Gill
    Intellectual 590 points

    Hi Neeraj,

    Your thought proves right !

    We changed the delay to 1ms and both systems pass the FG calibration.

    Is there a reason you suggested a delay of 100msec? (datasheet states 750ns).

    Should 1ms be fine? Should we use 100ms or is it advisable to poll bit '0' in register 0x270?

    Is there any documentation for this register and other reserved registers?

    Thanks

    Gil

  • +1 in reply to Gil Hershman71
    TI__Mastermind 20541 points

    Hi Gil,

    The fuse load speed is based on the dev clock frequency applied to ADC. If no dev clock is applied to the ADC the fuse will load using much internal clock. 

    I think the best option would be to poll bit '0' in register 0x270. Here is the documentation from ADC12DJ5200RF data sheet.

    Regards,

    Neeraj