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AFE5828: AFE5828 work on Pattern Mode(Sync )

Part Number: AFE5828

Hi All,

Hope AFE5828 work on Sync (half frame 1, half frame 0) , 111111000000  12bit

SPI set 12bit or 14bit is OK ,dclk output 360M or 420M

Register Sync (half frame 1, half frame 0) :

ADDR1:0014;//0000 0000 0001 0100
ADDR2:0080;//0000 0000 1000 0000// 0800 = half frame
ADDR3:1010;//0001 0000 0001 0000//12bit DIG_GAIN_EN=1
ADDR4:0000;//00 = 12-bit resolution

LVDS output still low

Best Regards,

Charlie

  • Hi Charlie,

    Thanks for sharing your concern.

    I looked at the settings you are writing. This looks fine to me. Ideally you should observe the sync pattern on all lvds data lines.

    One thing I am suspecting is whether the SPI write operation is happening or not? 

    Reasons could be:

    1. Check SPI write is working. (Either look at the data read back from the register or change the clk_rate/serialization rate  and probe if the clock is actually changed)

    2. Whether you are looking at FPGA output or probing through the scope? I would recommend to probe the data lines as well. 

    3. Please verify that you have the termination resistance of 100 ohms on the P and M output pins. If the termination resistance is not there, it wont work.

    Thanks and regards,

    Abhishek

  • Hi Charlie,

    At this point, it is unclear to me whether your issue is resolved. If so, please let me know if I can close this thread.

    If not, please share how may I help you to resolve your concern.

    Thanks & regards,

    Abhishek