ADS4225EVM: Not all signal bits arrive to fpga

Hi Alejandro,

I am checking into this and will get back to you soon. 

Regards, Amy

Hi Alejandro,

Could you check to see if the amplitude of the clock signal is at the level you expect? 

You can also check that the clock data format is in agreement with the FPGA's clock expected format. Please refer to pg. 7 and Table 10 of the datasheet for the SEN Control Pin.

https://www.ti.com/lit/ds/symlink/ads4225.pdf?ts=1637013539492&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FADS4225 

Regards, Amy

Clock configuration is ok. The CC pins expect .450v lvds swing. one of the adc options, so it's compatible and clock waveform at that pin appears to be correct. Also, I placed an ILA and a PLL in the fpga using the clock, and both fpga devices report no problems with clock.
What other issue can be? can a faulty power rail (3.3, 1.8, 1.2) make signal unable to arrive properly formed to fpga? this power rail can be the power source of one of the fpga I/O banks?
I can also show my code, it's still far from final application, so no copyright is involved yet

Thanks

Hi Alejandro,

Can you confirm that SPI writes are going through to the ADC by 1) issuing a power down SPI write and 2) confirming that the current on the EVM power supply goes down? It would also be good to probe the LVDS data outputs to see if there is activity.

Faulty power rails could be an issue, if 1.8V ADC LVDS data lines are going to a 3.3V bank.

Regards, Amy

Thanks for the advice Amy. Current does not go down when the software send the "Powerdown" command. It starts with .450A, but it remains still after "Powerdown" or "Suspend". Is there another measurement or test I can do?

Regards,
Alejandro Estay

Hi Alejandro,

If the current remains unchanged with the global powerdown command, this indicates read/write issues with the SPI commands. I setup the ADS4225 with a TSW1400 capture card in our lab and captured a ramp test pattern.

Here are things to check:

1. Board jumpers
   1. Check that the jumpers are configured as described in the EVM user guide page 5, section 2.2: https://www.ti.com/lit/ug/slau333a/slau333a.pdf?ts=1637600064322&ref_url=https%253A%252F%252Fwww.ti.com%252Ftool%252FADS4225EVM
   2. I attached a picture of my jumper configuration for you to double check.

Once you have confirmed that the jumpers are correctly set, try the global powerdown command again. On my board, the current decreases about 140 mA (from 680 mA to 540 mA) when this option is toggled.

The other register writes that are needed to get the ramp test pattern capture:

1. Digital Function Enable
   1. Toggle to 'Enabled'
   2. See datasheet pg. 56, section 9.3.3: https://www.ti.com/lit/ds/symlink/ads4225.pdf?ts=1637601761762&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FADS4225
2. Data Format
   1. Toggle to Offset Binary
3. Test Patterns
   1. Select Ramp

Let us know if you have other questions once you try these things out.

Regards, Amy

Jumpers are apparently correct, but still spi commands are not working. SPI pins show activity, but there's only some subtle blinks. I check the "Readout" switch to get periodic updates and there's no periodic read activity in the pins.

Hi Alejandro,

Can you verify that the SPI voltage signal levels and the setup and hold times are consistent with the ADS4225 datasheet?

https://www.ti.com/lit/ds/symlink/ads4225.pdf?ts=1637694417880&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FADS4225

Regards, Amy

Hi Alejandro,

Here is another thought:

Try configuring the ADS4225EVM with the TI GUI first, instead of trying to control it with the FPGA. You can download it from the TI site here:

• ADS42xxx SPI GUI (Rev. B)– SBAC113B.ZIP

https://www.ti.com/tool/ADS4225EVM#tech-docs

Once this is up and running, switch back to the FPGA SPI interface. If you have already tried this, trying comparing the voltage levels of the SPI signals when using the TI GUI vs. using the FPGA.

Another option would be to use parallel programming mode for the ADC, which would allow the board to be configured without SPI. However, you would need to ensure that the FPGA interface is working before attempting any external SPI testing.

Regards, Amy

To this moment i'm only controlling the ADC board with the GUI, and not from fpga. Can this serial interface malfunction be related to a problem with USB interface (FTDI)?

Hi Alejandro,

To ensure that it is not a board issue, you can try running the board in parallel mode. Also, be sure to run the GUI as a 'system administrator'.

Have you tried looking at the Device Manager to see if the USB is making a connection? You should see ‘USB Serial Converter’ listed under ‘Universal Serial Bus controllers’. If you unplug the USB, the device manager should blink. If this is not the case, it would be good to try a different USB port and/or cable.

Regards, Amy

Thank you for your avice amy. Apparently was a misplaced jumper. Now i'm getting all bits into th fpga. They are not aligned so far, but I think is workable

(the B channel is being tested with 1's pattern and all bits arrive. The upper is being tested with ramp. Is not a ramp, clearly, but is getting closer).

In the ramp pattern all bits are used?

Thanks

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I switched boards (i have another nexys video) and some bits are "frozen". I switched back and another group of bits are frozen too. Can this be a problem with the FMC connection adapter? or is just problems with clock phase and adjustment in the fpga code?