Clear DAC function is not as expected

Peng Wang

Part Number: DAC81416

Hi,

We are using DAC81416 in our design, the DAC is configured as single end mode, output range is 0~20V.

We are planing to use clear DAC function to force DAC output 0V.

In the datasheet, the output should be forced to zero code (0V in our configuration) when /CLR pin is active, but in our design when /CLR pin acitve (low voltage), the output hold to 20V, not zero code (0V) as expected.

If there any other configuration needed to make the clear function work ?

BR/Wang Peng

over 3 years ago

0 Akhilesh K over 3 years ago

TI__Mastermind 19086 points

Hi,

May I know what are these scope shots? blue is /CLR?

Please share the sequence of operation after power up.

Regards,

0 Peng Wang over 3 years ago in reply to Akhilesh K

Prodigy 90 points

Hi,

Bule is /CLR.

The DAC is configured in 7 basic steps:

1. Configure the SPICONFIG to power on the DAC device and enable the streaming mode. Write x"0A8C" to address 03.

2. Configure the SYNCCONFIG to enable the synchronous output mode. Write x"FFFF" to address 06.

3-6. Configure the DACRANGEn to set the output range to 0~20V. Write x"2222" to address 0A, 0B, 0C, 0D respectively

7. Configure the DACPWDWN to power on single channels accordingly. Write data from cpu (channel enable ) to address 09.

After configuration, send data to DAC address 10 each basic cycle and assert the LDAC pin after transmission. The data updated cycle is is 10us.

The clear signal might assert at the end of a basic cycle, after about 60ns LDAC pin asserted.

BR/Wang Peng

0 Akhilesh K over 3 years ago in reply to Peng Wang

TI__Mastermind 19086 points

Hi,

Basically you are issuing /CLR command after LDAC is asserted right (Low)? what is the status of /CS signal when you are applying /CLR? Do you wait for the outputs to be settled before applying /CLR command?

We need min 40ns between /CS rising edge to /CLR falling edge.

Regards,

0 Akhilesh K over 3 years ago in reply to Akhilesh K

TI__Mastermind 19086 points

Hi,

You need to wait minimum of 2.4uS before applying /CLR command after LDAC. Basically /CLR command acts as another DAC update. So you need to adhere to tDACWAIT in datasheet specifications.

Otherwise device will ignore this /CLR command.

Hope this clarifies your query.

Regards,

0 Peng Wang over 3 years ago in reply to Akhilesh K

Prodigy 90 points

Hi，

Acutally when /CLR is acitive(Low), the LDAC is already de-asserted(High), /CS signal is High voltage. The time between /CS rising edge and /CLR falling edge exceeds 80ns.

BR/Wang Peng

0 Peng Wang over 3 years ago in reply to Akhilesh K

Prodigy 90 points

Hi,

In following picture, the status of LDAC signal is drawned, it is applied before /CLR command. 250ms after /CLR become active, the output still keep 20V.

/CLR command acts as another DAC update, is that mean the LDAC signal should be acitved (low voltage) when /CLR command is issuing ?

BR/Wang Peng

0 Akhilesh K over 3 years ago in reply to Peng Wang

TI__Mastermind 19086 points

Hi,

After /LDAC low you need to wait min 2.5uS before applying /CLR command.

Please see the below diagram for more understanding.

Regards,

0 Peng Wang over 3 years ago in reply to Akhilesh K

Prodigy 90 points

Hi,

So you mean the negative edge of /CLR signal should wait 2.5ns after /LDAC, the clear function is triggered by falling edge of /CLR not only low voltage.

BR/Wang Peng