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DAC38RF82EVM: Reference design for Intel Arria 10

S Majumdar
Prodigy 30 points
Part Number: DAC38RF82EVM

Hi,

I am trying to use the available Arria 10 reference design for Arria 10 SoC device. The SYNC signal is supposed to come from the DAC EVM and it should be an input for the FPGA. The top design has an input signal named tx_syncn. It is connected to the FPGA pin E24. E24 is connected to an SMA connector named SMA_CLK_OUT (as shown in the schematic of the Arria 10 kit). How the SYNC signal is coming to the FPGA from the DAC? Should it not come from the DAC through the FMC?

What am I missing here? Please help.  

Regards,

S. Majumdar

  • 0
    TI__Mastermind 20541 points

    Hi S,

    The sync signal from the DAC on DAC EVM is routed to pin F10,F11 and F19,F20 on the FMC connector on the DAC EVM. These pins should be mapped with FMC connector on FPGA EVM accordingly 

    Regards,

    Neeraj 

  • 0 in reply to Neeraj Gill
    Prodigy 30 points

    Hi Neeraj,

    Thanks for confirming. But the reference design, provided by TI, does not have any SYNC input signal coming from the FMC! It has an input signal named tx_syncn coming from an SMA connector named SMA_CLK_OUT. But it is supposed to be a working design. So, I must be missing something here. Please help me to understand. I am trying to modify this design to work with Arria 10 SoC. So this information is very crucial for me.

    Regards,

    S. Majumdar

  • 0 in reply to Neeraj Gill
    Prodigy 30 points

    Hi Neeraj,

    The reference design (slac771a) is supposed to work with Arria 10 dev. kit. The schematic of this kit shows no connection for pins F10, F11, F19 and F20 of the FMC. Then how the sync signal is reaching the FPGA from the DAC evm?

    Regards,

    S. Majumdar

  • +1 in reply to S Majumdar
    TI__Guru* 91947 points

    S. Majumdar,

    On the DAC, you will need to assign the SYNC to the GPO0 pin, using register 0x01 bits 15:14. The GPO0 pin is connected to J11 pin 3 on the DAC EVM. You will then need to use a cable to connect J11 pin 3 on the DAC EVM to the Arria 10 board SMA that is connected to FPGA pin E24. This is how we made the SYNC connection when testing these two boards together. E24 on the FPGA should be setup for 1.8V CMOS level.

    Regards,

    Jim   

  • 0 in reply to jim s
    Prodigy 30 points

    Dear Jim,

    Thanks a lot for clearing the confusion. I am using Arria 10 SoC board. F10, F11, F19 and F20 are connected to FPGA in this board. It seems, I can use F10, F11 (LVDS) for the SYNC. In that case I don't need to change anything in the DAC EVM.

    Thanks and regards,

    S. Majumdar