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ADS114S06: The output signal DOUT and SCLK

takazawa masataka
Prodigy 10 points
Part Number: ADS114S06
Other Parts Discussed in Thread: ADS114S08EVM, ADS124S08

Please tell me about the output signal DOUT.

Product model number: ADS114S06
Evaluation board: ADS114S08EVM

We measured 3-wire RTD on the evaluation board and observed SCLK and DOUT with an oscilloscope.
As a result, SCLK was observed for 8 cycles x 3 sets, and when compared with the digital output result, it seems that the DOUT signal read at the timing of the 1st and 2nd sets of SCLK matches the output result.

I saw the question here is what is the purpose of the third set of SCLKs.   At this time as well, some kind of DOUT signal is being output.

CH2: SCLK　CH3: DOUT

Since the ADS114S06 is a 16-bit AD converter, I thought that the output result would be only 2 sets of SCLK (8 cycles x 2 sets = 16 bits).

What is the purpose of the third set of SCLK?

best regarad.

  • 0
    TI__Guru** 113765 points

    Hi Takazawa,

    Welcome to the E2E forum!  Essentially the code for the ADS124S08 and ADS114S08EVMs is identical.  I don't recall which portion of the code differentiates between the two devices.  When reading the data directly (and not using the RDATA command) and if additional SCLKs are transmitted during the read cycle, the output buffer will wrap around and repeat the conversion data.  From the scope shot you can see that the first and third bytes are the same.

    You will also see a repeated byte if you were to issue the RDATA command.  However, in this case the first two bytes would be the same.

    The firmware code for the EVM encompasses all modes of operation so it is quite complicated.  When developing code you most likely would use a fixed mode of operation and when reading data directly would only need to read the first two bytes.  So your thinking is correct in that the 16-bit version of the device family only requires a 2 byte read of the conversion result.

    Best regards,

    Bob B