ADS131A02: AD converter data latency from sampling

Hisao Uchikoshi

Part Number: ADS131A02

Hi Experts,

I want to confirm the latency from ADC sampling to conversion data over SPI. ADS131A02 adopts SINC3 filter and additional one cycle is required to output the data over SPI. Below is my understanding so please let me confirm if this is correct.

Assuming f_data cycle is 15.625us. Since SINC3 filter is used, it is like calculating the average during the period conv1, conv2 and conv3. The output of SINC3 is outputted one conversion later. Is this understanding correct?

Regards,

Uchikoshi

over 3 years ago

+1 Ryan Andrews over 3 years ago

TI__Guru 66566 points

Hello Uchikoshi-san,

Thank you for your post.

Yes - the ADS131A02 requires one extra conversion period to output the results from the sinc3 filter because the data is double-buffered. However, I would not say that the conversion output is directly an average of 3 previous conversions since the sinc filter coefficients are not evenly weighted. It is not really possible to pinpoint a conversion output with an exact moment in time like you can do with a SAR ADC.

Best regards,

Ryan

0 Hisao Uchikoshi over 3 years ago in reply to Ryan Andrews

TI__Genius 14940 points

Hi Ryan,

Regarding the delay, I am referring to below white paper.

https://www.ti.com/lit/wp/slyy095a/slyy095a.pdf?ts=1637657677199

This white paper seems to say the delay can be calculated. Below is the example.

I want to know if this is the same for ADS131A02 and if so how can we calculate the delay?

Regards,

Uchikoshi

+1 Ryan Andrews over 3 years ago in reply to Hisao Uchikoshi

TI__Guru 66566 points

Hello Uchikoshi-san,

Yes, this delay will be a deterministic number of modulator clock periods. The delay in microseconds is given in Table 3 for fMOD = 2.048 MHz and 4.096 MHz. The customer can scale these delays for other modulator clock frequencies as well.

Regards,

Ryan

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ADS131A02: AD converter data latency from sampling