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ADC12DJ3200EVM: SYNC signal is always low

Part Number: ADC12DJ3200EVM
Other Parts Discussed in Thread: ADC12DJ3200, LMK04828

Hi team

I am doing interoperability test of ADC12DJ3200 with my FPGA. My sampling sampling frequency 1250 Msps and i am using JMODE 2. My line rate is 5 Gbps and LMK04828 generates 125 Mhz clock for my FPGA. While programming the ADC card and reading the ADC register address0x208, i see that SYNC signal is always low and JESD link never up. I believe my pin mapping between ADC and FPGA is correct but i feel my SYNC signal is the culprit. What checks do you suggest for this scenario? Please advice.

Regards

Rohit