DDC112: Minimum Time to Prepare Side for Integration

Clifford Greenblatt

Part Number: DDC112

In Application Bulletin AB-131 (SBAA024), in Table II on page 3, minimum time to prepare side for integration (t6) is stated as 240 clock periods. In the DDC112 data sheet (SBAS085B), Figure 13 on page 16, minimum time to prepare side for integration (t11) is stated as 24.0-microseconds for both 10-MHz and 15-MHz. 240 clock periods would be 24.0-microseconds at 10-MHz but would be only 16.0-microseconds at 15-MHz. Which figure should I believe, 240 clock periods or 24.0-microseconds? Clock frequency for my application is 8-MHz.

over 3 years ago

0 TCT over 3 years ago

TI__Genius 11550 points

Hi Clifford,

Thanks for the post.

It is best to follow the recommendation in the DDC112 datasheet for t₁₁ (>24µs for both CLK = 10MHz and 15MHz). The application bulletin t₆ clock period generalization mainly applies to the system clock, which is lower than the typical DDC112 system clock specification.

Thanks

-TC

+1 Clifford Greenblatt over 3 years ago in reply to TCT

Prodigy 90 points

The system clock in my application is 8-MHz. If I go by the application bulletin, then 240 clock periods would be 30-microseconds. So, the 24-microseconds specified in the data sheet would not be sufficient to ensure the side is prepared for integration. In my 8-MHz system clock case, would I be wise to go by the application bulletin just to be safe?

0 TCT over 3 years ago in reply to Clifford Greenblatt

TI__Genius 11550 points

Hi Clifford,

Yes, for your 8-MHz system clock, you can use the application bulletin 240 clock periods or 30µs in your system design.

Thanks

-TC

0 Clifford Greenblatt over 3 years ago in reply to TCT

Prodigy 90 points

Thanks.

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DDC112: Minimum Time to Prepare Side for Integration