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ADS52J90: Interfacing SYNC~

Amy Luo
Expert 6895 points
Part Number: ADS52J90

Hi team,

When connecting SYSREF and SYNC, level matching needs to be considered. I see the following connection method in the following FAQ, that is, both SYSREF and SYNC use AC coupling. However, in ADS52J90 datasheet, figure 82 indicates AC coupling scheme for sysref (do not use for sync ~)

[FAQ] ADS52J90: How to terminate SYNC_SERDES, SYSREF_SERDES signals in ADS52J90?：https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/711635/faq-ads52j90-how-to-terminate-sync_serdes-sysref_serdes-signals-in-ads52j90?tisearch=e2e-sitesearch&keymatch=ADS52J90

The FAQ conflicts with the description in the ADS52J90 datasheet. I would like to know which one is correct.

Best Regards,

Amy Luo

  • 0
    TI__Expert 6895 points

    Hi

    Do you have any update on the issue

    Best Regards,

    Amy Luo

  • 0
    TI__Expert 6980 points

    Hi Amy,

    Apologies for the delayed response. Please find my response for both SYNC and SYSREF interfacing with FPGA.

    Interfacing SYNC with FPGA

    Since SYNC is a non periodic signal, there is no need to have direct AC coupling, but you have to match the common mode. The SYNCP and SYNCM pins have internal reference voltage of 0.7 V 

    In the datasheet, Figure 81 shows the circuit to level-shift from a 1.2-V common-mode voltage at the driver output to the 0.7 V at the ADC input. The resistance 3.57k and 5k on both positive and negative side provides this voltage drop and the 33nF cap in parallel to 3.57k provides coupling to transients. Please refer to the image below:

    Interfacing SYSREF with FPGA

    The SYSREF pins will require AC coupled input. The figure 82 on the datasheet is the correct one.

    Let me know if you have any further questions.

    Thanks & regards,

    Abhishek

  • 0 in reply to Abhishek Vishwa1
    TI__Expert 6895 points

    Hi Abhishek,

    Is it OK for SYNC to use direct AC coupling in FAQ?

    In the schematic diagram of EVM, SYSREF from LMK to ADC only uses 0.1uF and 100 ohm termination, and SYNC from FPGA to ADC only uses 100 ohm termination without level conversion. Is there a problem when the customer uses EVM connection when designing the circuit?

    Best Regards,

    Amy Luo

  • +1 in reply to Amy Luo
    TI__Expert 6980 points

    Hi Amy,

    As I mentioned earlier, sysref and sync input circuits are different due to the nature of each signal. SYSREF is a pulse signal, AC coupling through capacitor will work in that.

    However SYNC is kind of a longer signal and hence it needs common mode match and direct coupling. 

    The datasheet recommends the correct way to implement these. The EVM schematic is wrong, it works somehow but the functionality is not guaranteed. I will convey the same information to update the schematic of the EVM.

    Thanks & regards,

    Abhishek

  • 0 in reply to Abhishek Vishwa1
    TI__Expert 6980 points

    Hi Amy,

    For this situation, it is difficult for me to be certain the issue is resolved, can you confirm? 

    If not, do let me know if you need more explanation about the said topic.

    Regards,

    Abhishek