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Original question:

DAC38J84EVM: Questions for DAC design with a 3rd party evaluation FPGA board

DAC38J84EVM: SYNC signal of JESD204B PIN at FMC is not connected

shuai wang
Prodigy 40 points
Part Number: DAC38J84EVM
Other Parts Discussed in Thread: DAC38J84

DEAR TI,

I am using a third party alinx xczu9eg ultrascale+mpsoc development board for JESD204B based DA development(DAC38J84EVM), The FMC daughter board I am using is DAC38J84EVM , where the synchronization signal SYNCBP/N of the DAC chip is connected to the F10,F11 interface of the FMC while other sync，SYNCAB,SYNCCB is also at the F row.

The critical problem is, i found the f row of my  third party  FPGA evaluation board is grounded!

Is there any way that I can overcome this?

best regards.

Shuai

  • 0
    TI__Guru* 78194 points

    Hi,

    You can try to flywire the J21 CMOS SYNC signals to your FPGA. You can configure it through software through option below

    Schematic location

    FYI. This is not a standard FMC compatible design FPGA. All Xilinx FPGAs should have this port routed per VITA 57 spec.

  • 0 in reply to Kang Hsia
    Prodigy 40 points
    Kang Hsia said:
    FPGA

    Dear Kang:

    I'm confused about the I/O std of the signal from DAC38J84EVM through FMC(or Fly wire as you said).
    I could only find the SYNC_AB is a CMOS signal ,but what's the voltage standard? Is it LVCMOS33 or LVCOMS18 or something else?
    Also how should I configure the input signal voltage standard of SYNC_AB if I using wires to connect the port SYNC_AB and a port from 3.3V GPIO?

    ALSO,I'm very confused by the IO std of sysref_p/n, refclk_p/n , and tx_p/n[7:0] in particular.
    It seems I could not select the I/O std in vivado I/O ports menu.

    please help and give some advise.

    best regards.

  • +1 in reply to shuai wang
    TI__Guru* 78194 points

    Hi,

    You may refer to the datasheet Digital IO specification for detail:

    IO for DAC38j84 is 1.8V. You can use level translator parts for 3.3V to 1.8V conversion.