ADC3643: Questions about ADC3643

Hi ttd.

ttd said:

Q1 In 8.5 on page 43 of the data sheet, it is stated that it can be operated in the default mode without being controlled by SPI. What is the default interface mode?

The default configuration is set by the REFBUF voltage, and is selected by the user. The default choices are represented in table 8-11 on page 43. There is an internal pull-up resistor on the REFBUF circuit, so the TRUE default is represented by the row with (>1.7V).

ttd said:

Q2 Is the default value of the register the value listed in the Reset column of each register value table?
Also, is the default state different from the default value in the register?

Yes, the default value of the register is located in the Reset column. The default interface for the ADC3643 is DDR, unless the REFBUF pin is pulled < 0.1V (see table 8-1). A note will be made in the data sheet to clarify on the next revision.

ttd said:

Q3 What is the state of the pins before DCLKIN selects 2wire mode in SPI (In, Out, Hi-Z)?
If it is Out when the power is turned on, do we need to be able to avoid output collisions?

On power up, the ADC will load the output interface. If DDR, then no DCLKIN is required, and this pin will act as a CMOS output. If 2W serial mode is to be used, then the REFBUF pin should be pulled low (<0.1V) to ensure that the DCLKIN pin is not acting as a driver. SPI configuration can then be done to change other parameters, as required.

ttd said:

Q4 Regarding the explanation of Bit0 of register 0x13 on page 51, is 0x12 in the part of "... Register 0x07 along with the E-FUSE Load (0x12, D0) ..." a typo of 0x13?

This is a typo, and should be 0x13.

ttd said:

Q5 Regarding REFBUF, if the differential clock is set by External reference and the 2wire mode is set by SPI, is 8.5.1 on page 43 particularly irrelevant?

The REFBUF pin allows the option to not use SPI for some basic settings. SPI will overwrite any actions that the REFBUF pin sets. This section is still relevant since some customers will not want to use SPI. If not using the REFBUF pin, please supply 1.8VDC+.

ttd said:

Q6 InitializeSetUp on page 64 requires 200,000 clocks for calibration. Do I need DCLKIN at this time?

No, DCLKIN is not required for ADC start-up calibration.

Best Regards,

Dan

Hi ttd,

ttd said:

Q7. Single Ended Clock Input is TBD on page 26 . Is it 0x0E?

       Single Ended Clock Input: This mode needs to be configured using SPI register TBD.

Yes, this should be register 0xE.

ttd said:

Q8  I would like to consider using the AC coupling differential clock, external 1.6V reference, and 2wire mode.

When REFBUF is connected to GND and booted, SPI SEN is enabled after setting the clock to 2000000 for calibration. (See Figure 10-1 on page 64)
Although it is a differential clock on the circuit, the default setting is single-ended, so should the clock to be output first be output only on the CLKP side?
(The CLKN side will be connected to 0V with a capacitor. After setting it differentially with SPI, the CLKN side will also output) "

The default setting is single-ended if there is not a voltage forced on the REFBUF pin, due to the internal weak pull up resistor to AVDD (1.8V). If you are forcing < 0.1V to  the REFBUF pin, the default setting is in fact a differential clock input. In essence, you control the default state of the ADC with this REFBUF pin, and can modify additional settings with SPI interface after calibration (if necessary).

ttd said:

Q9 I want to use AC coupling differential clock, external 1.6V reference, 2wire mode.
When I connect the REFBUF to GND and start it, it goes into the internal reference mode. Is it okay to supply a 1.6V reference from the outside?

I would recommend that you not drive the VREF pin with an external 1.6V source if the ADC is in internal reference mode. It looks like there is not a REFBUG pin state that will correspond directly to your needs. My suggestion is to utilize the 1.8V state (differential clock, external reference, DDR), and then change the output interface to 2-Wire mode via SPI after calibration is complete.

Best Regards,

Dan

Hi ttd,

To avoid two driving sources on the multi-function pin (DB1, CMOS data output/DCLKIN serial input) while using 1.8V on the REFBUF pin, I would recommend putting the DCLKIN driver (from the FPGA/Processor/ClockingTree/etc...) in a standby or tri-state mode while the ADC is going through its initial configuration. Once you have configured the ADC data interface from DDR mode to the 2Wire serial mode, then the DCLKIN driver can be enabled.

Best Regards,

Dan

Hi ttd,

I think I mis-spoke with my response to question 8. With the REFBUF pin pulled high (1.8V), then the clock input is differential. Please let me know if there is another questions here.

Best Regards,

Dan

Hi ttd,

The full-scale input is for differential inputs. So, Vp - (-)Vm = 2.25Vpp. I believe that (1) is the correct interpretation.

Best Regards,

Dan