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ADS8689: SPI transactions and timing

ArTzy
Genius 17475 points
Part Number: ADS8689

Hi Experts,

Good day. I am posting this on behalf of my client query about ADS8689:

I am trying to correlate where the specification for tacq in the table in section 6.6 of the datasheet.  If it takes 32 SCLK's to clock the data out of the device on the SPI bus, then if running SCK at any frequency above 6.4 MHz there will be some required 'dead time where SCK stops for some period before the rising edge of CONVST/CS.  The datasheet is totally lacking in showing the SPI transactions from start to finish for one Frame.

Thank you for your support.

Regards,
Archie A.

  • 0
    TI__Mastermind 45645 points

    Hi Archie A.,

    The datasheet has clearly showed the timing parameter and specification tHT_CKCS which is the delay time between the last SCLK edge to CONVST/CS rising edge, please see the tHT_CKCS in the entire timing in the Figure 6-3/6-4/6-5/6-6.

    Regards,

    Dale