DAC81416: Registers not updating with one exception. Can read.

Hi Carlo,

Can you have the customer read all of the registers and let me know the values stored in each? It sounds like the SPI read and write are working since they are able to write to the BRDCONFIG register. Maybe they have the incorrect config settings. 

Is it also possible to share a schematic? Is the internal reference being used? What are the supply voltages? 

Best,

Katlynne Jones

Hello Katlynne,

To answer the questions, when reading the registers, it appears they are all the default values as specified by the datasheet. The BRDCONFIG register reads as the default value until we write to it, after which it reads to us the value we wrote. We are trying to use the internal reference but that is not on by default as far as the datasheet is concerned and as far as I can tell during testing. I have attached a schematic image below. Two of our chips are operating with a DAC_ANALOG_HIGH and DAC_ANALOG_LOW of +20V and -20V respectively. We also have a DAC that we are giving these values to +/-5V, which is a mistake but the problem we are facing is the same on all 3 DACs which makes me think that is an unrelated issue that we will handle on our own. DAC_REF net goes to a pin header so we can check it. LDAC, RESET, CLR, SDO, SDI, SCK, and CS are all sent to an FPGA where we are trying to set everything up from. We double checked that LDAC, RESET, and CLR are at the appropriate levels.

Let me know if you need other details.

Regards,
Carlo

Hi Carlo,

We will have to take a look at this when we're back in the office on the third.

Thanks,

Paul

Hi Carlo,

I am confirming with the design team, but I suspect that the DAC data registers are write only which would explain why you are able to read from some registers and not the data registers. Please let me know what the customer was writing to CONFIG registers. A 0 needs to be written to the REF-PWDWN bit in the GENCONFIG register to power on the internal reference. The DACs are powered down by default, so 0x0000 needs to be written to the DACPWDWN register. They can start with the default range of 0 to 5V in the DACRANGE register. Were there any other settings they were trying to write? 

Have them try the above settings and let me know if they are able to see the internal reference on their DAC_REF test point. 

Best,

Katlynne Jones

Hello Katlynne,

Please see the response of our customer as follows:

Let me know if you need other details.

Regards,
Carlo

Hi,

DATA registers are Write only (0x10 to 0x1F).

Your configuration seems correct to me except for SPI_CONFIG.

SPI_CONFIG you need to write 0x0A84 to enable SDO and to enable Device.

You dont need to write GEN_CONFIG twice.

After the configuration, send DAC_DATA to see if you are getting the voltage output.

Regards,

AK

Hello AK,

Our customer is using FSDO, thus the SPICONFIG Register gets configured to 0A86 rather than 0A84. Can you please clarify what you are referring to with the DATA registers: does this refer to the DACn registers? Please see the other details of our customer's response below:

I am struggling with several other registers I can not write to. Namely the DACRANGEn, DACPWRDWN, and DACn registers which all aren't changing from their default values on startup.

Additionally the GENCONFIG register is now returning 0000 which is surprising to me as I expected the reserved bits to be the same for that register and the value I write keeps those reserved bits intact. I am able to see the internal reference on the pin now though.

I have attached screenshots from the datasheet for what registers I am referring to if that helps.


Addendum:

The STATUS register is also returning 0008. I am not sure what this means because the datasheet refers to that nonzero bit as a reserved bit. I was hoping it was an alarm that would tell me something is going wrong but it just says reserved in the datasheet.

Regards,
Carlo

Hi Carlo,

The DACn-DATA registers are write only (this is a typo in the datasheet). They will return 0 if you try to read them. The DACRANGE register is also write only, this is mentioned in the datasheet here:

It is possible that the DACPWDN register is also write only. I am trying to confirm this with the designers. 

Has the customer tried writing the sequence you shared in the previous post and checking the output? I wouldn't rely on reading back those registers until I can confirm which registers are actually readable. 

I will also check with the designers to see if the 0x0008 in the status register means anything. 

Best,

Katlynne Jones

Hi Carlo,

the STATUS register reading 0x0008 is normal. The DACPWDN is R/W so the customer should be able to read back 0x0000 after powering-on all of the DAC channels. I've confirmed with the design team that DACn-DATA, BRDCASR, and DACRANGE are write only registers. 

Best,

Katlynne Jones

Hello Katlynne,

Regards,
Carlo

Hi Carlo,

GENCONFIG should power on the internal reference and the DIFF-EN bits should be left default to disable differential output mode. 

BRDCONFIG should be left as its default (0xFFFF) if you would like the BRDCAST register to update the DAC channels. Otherwise set the EN to 0 for each channel you don't want to be updated by the BRDCAST register.

SYNCCONFIG should be left as its default value (0x0000) for the channels to update in asynchronous mode. 

TOGGCONFIG0/1 should be left as its default value (0x0000) unless you want to use the toggle feature. 

DACPWDN should be set to 0x0000 to power on all channels. 

DACRANGEn should be set to the appropriate range. You can try leaving at the default (0x0000) for debugging purposes. 

BRDCAST is used to set the output for all channels with the DACn-BRDCAST-EN set to 1. 

DACn is used to set the output for its corresponding output channel. 

These registers all pertain to setting the DAC outputs. It may be helpful for the customer to send a scope shot of their write and read of the DACPWDN register with the CS, SCLK, and SDI lines included. Maybe there is something in their SPI communication that is causing that register not to update. 

Are there currently any loads connected to the DAC outputs? 

Best,

Katlynne Jones

Try having the customer write only:

0x3 0x0086

0x4 0x3F00

0x9 0x0000

0xF 0xFFFF

Leave everything else as default. This should set all DAC outputs to 5V via the broadcast register. 

Hello Katlynne,

Regards,
Carlo

Hi Carlo,

Please have the customer send a scope shot of their write and read of the DACPWDN register with the CS, SCLK, and SDI lines included. There could be something in their SPI communication that is causing that register not to update. I have seen that sometimes the incorrect SPI mode settings allow for communication with some registers and not others. 

Another thought is that the internal reference should be very close to 2.5V:

You mentioned that the customer measured this at 2.4V. Can you have them double check again? Can you also confirm that the supplies are at the ±20V and the LDAC, CLR, RESET are being held at the expected VIO voltage (3.3V in the customer schematic). 

Best,

Katlynne Jones

Hello Katlynne,

Please see the response below.

I have included below a scope image of trying to write to the PWRDWN register. The green plot if CS and that channel on the scope is busted so in such a way that it is permanently AC Coupled. Purple is slave out (I am not reading in this case, it should just echo the write command I send), red is master out/slave in, and yellow is SCLK. I have also attached it in csv format should you want that format at all.

scope_2.csv

I also checked and the VREF is 2.4V and LDAC, CLR, RESET are kept at 3.3V.

Regards,
Carlo

Hi Carlo,

Thank you for the scope shot and confirming those values. Looking at the scope shot, I'm either seeing the register address being written as 0xA or 0x5. The PWDWN register is address 0x9. Can you double check that they are writing to the correct register address? The SPI mode does look correct to me. 

Best,

Katlynne Jones

Hello Katlynne,

Our customer sent the wrong section of the signal for the PWRDWN register previously. Please see the correct one below.

Regards,
Carlo

Hi Carlo,

I am taking a look at this with my team. We'll get a response back to you soon. 

Best,

Katlynne Jones

Hi Carlo,

What is the customer's power supply capability? Specifically, the +5V, DAC_ANALOG_HIGH, and DAC_ANALOG_LOW current drive capability? When you enable the DACs from power down and/or have them change code while having some kind of resistive or capacitive load, you would expect an increase in the current consumption of the device, even it if it just momentarily (for the case of a capacitive load).  I am suspecting that when you enable the DACs, your supplies are collapsing for a short period forcing the device to reset.  Can you monitor these supply rails as you update?

Thanks,

Paul

Hello Paul,

Please see the response of our customer:

I checked the power supply and there isn't a noticeable rise in current when I try changing registers. Could also be the capacitors aren't able to keep up but I followed the datasheets recommendations I believe with the bypass, could you have the design team double check my schematic? Also since after attempted configuration some registers stay in their written configuration, does that mean a power on reset event is not happening? Can you double check with the design team for which registers are affected by power on reset?

Regards,
Carlo

I am checking on this now.

Hello Paul,

Please share an update. Thank you.

Regards,
Carlo

Hi Carlo, sorry for the delay.  I am still working out some details with the team.  I will have a response tomorrow.

Hi Carlo, 

Sorry for delay ,

We ordered EVM  to cross very behavior..  mostly i will get it by tomorrow. 

Also, i understand from the thread that customer can able to read device but writing not happing ? and can't get any output. 

meanwhile could you please ask customer to send write and read transfer snap.  i can see some snap in thread but which is not clear to me.

Send snap with SCLK, SDIN,SDO,SYNC, and LDACn  for both read and write.