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ADS54J64EVM: How to use custom ADC sampling rate using ADS54J64EVM and TSW14J56EVM

Keira Duffy
Prodigy 40 points
Part Number: ADS54J64EVM
Other Parts Discussed in Thread: LMK04828, ADS54J64

Hi,

I have both the ADS54J64EVM and TSW14J56EVM boards connected to each other and I have the example design running as described in section 2.2. I used my ZC706 Zynq-7 eval board to provide the 61.44MHz clock reference to the LK04828. Now I would like to put the LMK04828 into clock distribution mode per section 3.2 of ADS54K64EVM manual so that I can have the ADC sampling rate equal to the frequency at LMK_CLK_IN. The manual states that there is a Macro State Script LMK04828_config1.cfg to do this but it does not explain at all how to load it. The manual does state "If it is required to operate the LMK04828 device in clock distribution mode, the onboard VCXO must be disabled by removing the shorting jumper at JP2." which I can easily do but I am not sure how to program the LK04828 and the CPLD on the ADS54J64EVM to put the board into clock distribution mode and have the ADC sampling frequency at my LMK_CLK_IN frequency.

Thank you,

Keira

  • 0
    TI__Guru* 91947 points

    Keira,

    What you are attempting to do is not very easy to explain. Depending on the ADC sample rate you select, the TSW14J56 FPGA will determine the required external input frequency. In your case, if you want to sample the ADC with a 61.44MHz clock, the FPGA will requires a 122.88MHz clock. To run this test, apply 122.88MHz to J12 and follow the attached instructions. In most cases though, when using a higher sampling rate, the FPGA will need a slower clock. In these cases, the ADC would run at the same frequency as the input clock and the FPGA would use a divided down version. 

    Regards,

    Jim

    ADS54J64_LMK_CLK_DISTR.pptx

  • 0
    Prodigy 20 points

    Jim,

    Thank you for your quick response and I am sorry it has taken me so long to get back to this. The presentation you attached states to setup the AD54J64 using the intro tab but I am not exactly sure what this means for my setup. The buttons are labeled Mode0 +linearity. What is meant by the linearity setting or trim setting? What is the difference between Nyquist 1 and 2? The datasheet for the ADS54J64 explains how to set these but never explains what they mean. 

    If I am trying to set the ADC sample rate of 280MHz, are you saying that I should input 140Mhz into J12 of the ADS54J64EVM and setting the LMK04828 just as you have in the powerpoint? I followed your entire example for a ADC sample rate of 122.88Mhz but I am not sure why your last slide shows a new line rate of 614.4M in HSDC PRO. When I set additional device parameters to ADS Sampling rate  = 122.88M, input freq = 32.22M, NCO = 0, and decimation = 4 (since mode 0 has decimation = 4 and no NCO) I get a lane rate of 1.2288G. Does this make sense?

    I am not sure if the LMK04828 is just getting programmed with your setup or what but it doesn't seem to work. I do not have any LEDs on or flashing on the ADS54J64 board besides D2. I would think the LEDs near the LMK04828 would be flashing. I also get and error in HSDC Pro saying that there is no data. 

    thanks,

    Keira

  • 0 in reply to Keira Duffy
    TI__Guru* 91947 points

    Keira,

    The person who created this GUI is no longer with TI so I will not be able to answer all of your questions. What I think they meant by Mode0 + linearity is the button will load the mode followed by the required ADC calibration and trim loading. See tables 62 and 63 in the data sheet for more info about this. You can actually see what the buttons are doing by double left clicking on the word "idle" in the lower left of the GUI to open a log file that show all register writes that occur (see second slide in attached file). 

    The Nyquist 1 and Nyquist 2 buttons set certain registers to optimize the performance of the part depending on whether your input tone is in the first Nyquist or 2nd Nyquist zone.

    If you want to operate with a sample rate of 280MHz, you will need to apply this frequency to J12 and operate the LMK in clock distribution mode. See attached file for steps on how to run with external clock mode using mode 0.

    Regards,

    Jim

    ADS54J64_LMK_CLK_DISTR_280MHz.pptx

  • 0
    Prodigy 20 points

    Jim, thanks again for your response. It was very helpful! Hopefully one last question. I am using HSDC Pro to capture my data. I out the capture in continuos mode but cannot figure out where the data is being saved to. I don't want to use another program to read it, I just was minutes worth of data capture dumped into a csv file. How do I do this and where is my data being saved to?

    Thanks,

    Keira

  • 0 in reply to Keira Duffy
    TI__Guru* 91947 points

    Keira,

    If using continuous capture, only the last capture after you click on stop will be saved. The GUI writes the data the following location:

    C:\Users\Public\Public Documents\Texas Instruments\High Speed Data Converter Pro\HSDCPro Data

    There will be a .bin data file for each channel.

    The TSW14J56EVM can only store up to 2G 16 bit samples. In the GUI, to change the capture data size, go to the "Data Capture Options" tab, then select "Capture Options", then change the   # of samples (per channel) to the max value allowed. The default value is 65,536 samples.

    Depending on the mode used this could be as high as 2,147,483,648 samples for 1 channel mode or as low as 268,435,456 samples per channel in 8 channel mode. 

    Regards,

    Jim