• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 278 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC128S102: DOUT Signal Before Track State

Ray Vincent Aranzaso
Mastermind 18180 points
Part Number: ADC128S102

Hi,

Good Day. I have a customer who is working with ADC128S102. Please see below his query for your reference. Thank you very much.

I am working on the FPGA code to read signals from ADC128S102 part. The datasheet mentioned "The ADC's DOUT pin is in a high impedance state when CS is high and is active when CS is low".

DOUT pins is logic high or logic low when in high impedance state? Can i assume that DOUT pins is always logic high when CS is high and is always logic low when CS is low before the track state?

Best Regards,

Ray Vincent

  • 0
    TI__Guru**** 180831 points

    Hi Ray,

    DOUT is neither high nor low on the ADC128S102 /CS line is high.  It is in a high impedance state as the datasheet mentions.  This means the DOUT is essentially floating - there is nothing driving it to any particular logic level.  When you pull /CS low, the DOUT is driven low through the first four falling clock edges while the device is in track mode.