Hello,
according to page 43 of the datasheet, the clock can be driven by a single-ended CMOS clock. What signaling levels are best used for this purpose? 1.8V/2.5V/3.3 V LVCMOS/LVTTL?
(SNR degradation due to increased jitter is not an issue in our application)
Thanks a lot for your help,
have a nice day,
Bernd
