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DAC38RF84: EXTREF_ENA bit in "Divided Output Clock Configuration Register (CLK_OUT, 0x0C)"

Yao-Hua
Prodigy 120 points
Part Number: DAC38RF84


Hi, there :

Bit 0 of "Divided Output Clock Configuration Register" in DIG_MISC page is EXTREF_ENA.

The description says it allows the chip to use external reference or internal reference.

Does it mean CLK_OUT use either DACCLKP/N or internal PLL as the reference?

Does "EXTREF_ENA" have nothing to do with PLL_ENA (Register 0x31) & SERDES_REFCLK_SEL(Register 0x3B)?  

Please help to clarify & thanks.

Regards,

Yao-Hua

  • 0
    TI__Guru* 91947 points

    Yao-Hua,

    Register 0x0C EXTREF_ENA determines if the DAC uses the internal reference (0.9V) or an external reference. If using external reference, you would set this to "1" and provide a reference source to pin C10 (EXTIO).

    PLL_ENA in register 0x31 in page 4 determines if the DAC uses the external clock pins or the internal PLL. If set to "1", the PLL uses the source on the DACCLK input pins as a reference for the PLL and the PLL output is used as the DAC clock. If set to "0", the DAC uses either the single-ended clock input or differential clock input, which is determined by the setting of SEL_EXTCLK_DIFFSE in the same register.

    Regards,

    Jim